Datasheet LTC1750 (Analog Devices)
| Hersteller | Analog Devices |
| Beschreibung | 14-Bit, 80Msps Wide Bandwidth ADC |
| Seiten / Seite | 20 / 1 — FEATURES. DESCRIPTIO. Sample Rate: 80Msps. 500MHz Full Power Bandwidth … |
| Dateiformat / Größe | PDF / 288 Kb |
| Dokumentensprache | Englisch |
FEATURES. DESCRIPTIO. Sample Rate: 80Msps. 500MHz Full Power Bandwidth S/H. Direct IF Sampling Up to 500MHz
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LTC1750 14-Bit, 80Msps Wide Bandwidth ADC
U FEATURES DESCRIPTIO
■
Sample Rate: 80Msps
The LTC®1750 is an 80Msps, 14-bit A/D converter de- ■
500MHz Full Power Bandwidth S/H
signed for digitizing wide dynamic range signals up to ■
Direct IF Sampling Up to 500MHz
frequencies of 500MHz. The input range of the ADC can be ■
PGA Front End (2.25VP-P or 1.35VP-P Input Range)
optimized with the on-chip PGA sample-and-hold circuit ■
75.5dB SNR and 90dB SFDR (PGA = 0)
and flexible reference circuitry. ■
73dB SNR and 90dB SFDR (PGA = 1)
The LTC1750 has a highly linear sample-and-hold circuit ■ No Missing Codes with a bandwidth of 500MHz. The SFDR is 82dB with an ■ Single 5V Supply input frequency of 250MHz. Ultralow jitter of 0.12psRMS ■ Power Dissipation: 1.45W allows undersampling of IF frequencies with minimal ■ Two Pin Selectable Reference Values degradation in SNR. DC specs include ±3LSB INL and no ■ Two’s Complement or Offset Binary Outputs missing codes. ■ Out-of-Range Indicator ■ Data Ready Output Clock The digital interface is compatible with 5V, 3V, 2V and ■ Pin-for-Pin Family LVDS logic systems. The ENC and ENC inputs may be ■ 48-Pin TSSOP Package driven differentially from PECL, GTL and other low swing
U
logic families or from single-ended TTL or CMOS. The low
APPLICATIO S
noise, high gain ENC and ENC inputs may also be driven by a sinusoidal signal without degrading performance. A ■ Telecommunications separate output power supply can be operated from 0.5V ■ Receivers to 5V, making it easy to connect directly to any low voltage ■ Cellular Base Stations DSPs or FIFOs. ■ Spectrum Analysis ■ Imaging Systems The 48-pin TSSOP package with a flow-through pinout ■ MRI simplifies the board layout. ■ Tomography , LTC and LT are registered trademarks of Linear Technology Corporation.
W BLOCK DIAGRA 80Msps, 14-Bit ADC with a 2.25V Differential Input Range
PGA OVDD 0.5V TO 5V 0.1µF 0.1µF A + IN OF ±1.125V CORRECTION 14 D13 S/H 14-BIT DIFFERENTIAL LOGIC AND OUTPUT • • – CIRCUIT PIPELINED ADC ANALOG INPUT A SHIFT LATCHES • IN D0 REGISTER CLKOUT SENSE OGND BUFFER VDD 5V RANGE 1µF 1µF 1µF SELECT DIFF AMP VCM GND 2VREF CONTROL LOGIC 4.7µF 1750 BD REFLB REFHA REFLA REFHB ENC ENC MSBINV 4.7µF 0.1µF 0.1µF DIFFERENTIAL 1µF 1µF ENCODE INPUT 1750f 1
U FEATURES DESCRIPTIO
■
Sample Rate: 80Msps
The LTC®1750 is an 80Msps, 14-bit A/D converter de- ■
500MHz Full Power Bandwidth S/H
signed for digitizing wide dynamic range signals up to ■
Direct IF Sampling Up to 500MHz
frequencies of 500MHz. The input range of the ADC can be ■
PGA Front End (2.25VP-P or 1.35VP-P Input Range)
optimized with the on-chip PGA sample-and-hold circuit ■
75.5dB SNR and 90dB SFDR (PGA = 0)
and flexible reference circuitry. ■
73dB SNR and 90dB SFDR (PGA = 1)
The LTC1750 has a highly linear sample-and-hold circuit ■ No Missing Codes with a bandwidth of 500MHz. The SFDR is 82dB with an ■ Single 5V Supply input frequency of 250MHz. Ultralow jitter of 0.12psRMS ■ Power Dissipation: 1.45W allows undersampling of IF frequencies with minimal ■ Two Pin Selectable Reference Values degradation in SNR. DC specs include ±3LSB INL and no ■ Two’s Complement or Offset Binary Outputs missing codes. ■ Out-of-Range Indicator ■ Data Ready Output Clock The digital interface is compatible with 5V, 3V, 2V and ■ Pin-for-Pin Family LVDS logic systems. The ENC and ENC inputs may be ■ 48-Pin TSSOP Package driven differentially from PECL, GTL and other low swing
U
logic families or from single-ended TTL or CMOS. The low
APPLICATIO S
noise, high gain ENC and ENC inputs may also be driven by a sinusoidal signal without degrading performance. A ■ Telecommunications separate output power supply can be operated from 0.5V ■ Receivers to 5V, making it easy to connect directly to any low voltage ■ Cellular Base Stations DSPs or FIFOs. ■ Spectrum Analysis ■ Imaging Systems The 48-pin TSSOP package with a flow-through pinout ■ MRI simplifies the board layout. ■ Tomography , LTC and LT are registered trademarks of Linear Technology Corporation.
W BLOCK DIAGRA 80Msps, 14-Bit ADC with a 2.25V Differential Input Range
PGA OVDD 0.5V TO 5V 0.1µF 0.1µF A + IN OF ±1.125V CORRECTION 14 D13 S/H 14-BIT DIFFERENTIAL LOGIC AND OUTPUT • • – CIRCUIT PIPELINED ADC ANALOG INPUT A SHIFT LATCHES • IN D0 REGISTER CLKOUT SENSE OGND BUFFER VDD 5V RANGE 1µF 1µF 1µF SELECT DIFF AMP VCM GND 2VREF CONTROL LOGIC 4.7µF 1750 BD REFLB REFHA REFLA REFHB ENC ENC MSBINV 4.7µF 0.1µF 0.1µF DIFFERENTIAL 1µF 1µF ENCODE INPUT 1750f 1