Datasheet LTC1747 (Analog Devices)
| Hersteller | Analog Devices |
| Beschreibung | 12-Bit, 80Msps Low Noise ADC |
| Seiten / Seite | 20 / 1 — FEATURES. DESCRIPTIO. Sample Rate: 80Msps. 72dB SNR and 85dB SFDR (3.2V … |
| Dateiformat / Größe | PDF / 504 Kb |
| Dokumentensprache | Englisch |
FEATURES. DESCRIPTIO. Sample Rate: 80Msps. 72dB SNR and 85dB SFDR (3.2V Range). 70.5dB SNR and 87dB SFDR (2V Range)
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LTC1747 12-Bit, 80Msps Low Noise ADC
U FEATURES DESCRIPTIO
■
Sample Rate: 80Msps
The LTC®1747 is an 80Msps, sampling 12-bit A/D con- ■
72dB SNR and 85dB SFDR (3.2V Range)
verter designed for digitizing high frequency, wide dy- ■
70.5dB SNR and 87dB SFDR (2V Range)
namic range signals. Pin selectable input ranges of ±1V ■
Pin Compatible with 14-Bit 80Msps LTC1748
and ±1.6V along with a resistor programmable mode ■ No Missing Codes allow the LTC1747’s input range to be optimized for a wide ■ Single 5V Supply variety of applications. ■ Power Dissipation: 1.4W The LTC1747 is perfect for demanding communications ■ Selectable Input Ranges: ±1V or ±1.6V applications with AC performance that includes 72dB ■ 240MHz Full Power Bandwidth S/H SNR and 85dB spurious free dynamic range. Ultralow jitter ■ Pin Compatible Family of 0.15ps 25Msps: LTC1746 (14-Bit), LTC1745 (12-Bit) RMS allows undersampling of IF frequencies with excellent noise performance. DC specs include ±1.5 LSB 50Msps: LTC1744 (14-Bit), LTC1743 (12-Bit) INL and ±0.8LSB DNL over temperature. 65Msps: LTC1742 (14-Bit), LTC1741 (12-Bit) 80Msps: LTC1748 (14-Bit), LTC1747 (12-Bit) The digital interface is compatible with 5V, 3V, 2V and ■ 48-Pin TSSOP Package LVDS logic systems. The ENC and ENC inputs may be
U
driven differentially from PECL, GTL and other low swing
APPLICATIO S
logic families or from single-ended TTL or CMOS. The low noise, high gain ENC and ENC inputs may also be driven ■ Telecommunications by a sinusoidal signal without degrading performance. A ■ Receivers separate output power supply can be operated from 0.5V ■ Cellular Base Stations to 5V, making it easy to connect directly to any low voltage ■ Spectrum Analysis DSPs or FIFOs. ■ Imaging Systems The TSSOP package with a flow-through pinout simplifies , LTC and LT are registered trademarks of Linear Technology Corporation. the board layout.
W BLOCK DIAGRA 80Msps, 12-Bit ADC with a 2V Differential Input Range
OVDD 0.5V TO 5V 0.1µF 0.1µF A + IN OF ±1V CORRECTION 12 D11 DIFFERENTIAL S/H 12-BIT LOGIC AND OUTPUT • • ANALOG INPUT AMP PIPELINED ADC SHIFT LATCHES • A – D0 IN REGISTER CLKOUT OGND SENSE BUFFER VDD 5V RANGE 1µF 1µF SELECT DIFF AMP 1µF VCM GND 2.35VREF CONTROL LOGIC 4.7µF 1747 BD REFLB REFHA REFLA REFHB ENC ENC MSBINV OE 4.7µF 0.1µF 0.1µF DIFFERENTIAL 1µF 1µF ENCODE INPUT 1747fa 1
U FEATURES DESCRIPTIO
■
Sample Rate: 80Msps
The LTC®1747 is an 80Msps, sampling 12-bit A/D con- ■
72dB SNR and 85dB SFDR (3.2V Range)
verter designed for digitizing high frequency, wide dy- ■
70.5dB SNR and 87dB SFDR (2V Range)
namic range signals. Pin selectable input ranges of ±1V ■
Pin Compatible with 14-Bit 80Msps LTC1748
and ±1.6V along with a resistor programmable mode ■ No Missing Codes allow the LTC1747’s input range to be optimized for a wide ■ Single 5V Supply variety of applications. ■ Power Dissipation: 1.4W The LTC1747 is perfect for demanding communications ■ Selectable Input Ranges: ±1V or ±1.6V applications with AC performance that includes 72dB ■ 240MHz Full Power Bandwidth S/H SNR and 85dB spurious free dynamic range. Ultralow jitter ■ Pin Compatible Family of 0.15ps 25Msps: LTC1746 (14-Bit), LTC1745 (12-Bit) RMS allows undersampling of IF frequencies with excellent noise performance. DC specs include ±1.5 LSB 50Msps: LTC1744 (14-Bit), LTC1743 (12-Bit) INL and ±0.8LSB DNL over temperature. 65Msps: LTC1742 (14-Bit), LTC1741 (12-Bit) 80Msps: LTC1748 (14-Bit), LTC1747 (12-Bit) The digital interface is compatible with 5V, 3V, 2V and ■ 48-Pin TSSOP Package LVDS logic systems. The ENC and ENC inputs may be
U
driven differentially from PECL, GTL and other low swing
APPLICATIO S
logic families or from single-ended TTL or CMOS. The low noise, high gain ENC and ENC inputs may also be driven ■ Telecommunications by a sinusoidal signal without degrading performance. A ■ Receivers separate output power supply can be operated from 0.5V ■ Cellular Base Stations to 5V, making it easy to connect directly to any low voltage ■ Spectrum Analysis DSPs or FIFOs. ■ Imaging Systems The TSSOP package with a flow-through pinout simplifies , LTC and LT are registered trademarks of Linear Technology Corporation. the board layout.
W BLOCK DIAGRA 80Msps, 12-Bit ADC with a 2V Differential Input Range
OVDD 0.5V TO 5V 0.1µF 0.1µF A + IN OF ±1V CORRECTION 12 D11 DIFFERENTIAL S/H 12-BIT LOGIC AND OUTPUT • • ANALOG INPUT AMP PIPELINED ADC SHIFT LATCHES • A – D0 IN REGISTER CLKOUT OGND SENSE BUFFER VDD 5V RANGE 1µF 1µF SELECT DIFF AMP 1µF VCM GND 2.35VREF CONTROL LOGIC 4.7µF 1747 BD REFLB REFHA REFLA REFHB ENC ENC MSBINV OE 4.7µF 0.1µF 0.1µF DIFFERENTIAL 1µF 1µF ENCODE INPUT 1747fa 1