Datasheet LTC1743 (Analog Devices)
| Hersteller | Analog Devices |
| Beschreibung | 12-Bit, 50Msps ADC |
| Seiten / Seite | 24 / 1 — FEATURES. DESCRIPTIO. Sample Rate: 50Msps. 72.5dB SNR and 85dB SFDR (3.2V … |
| Dateiformat / Größe | PDF / 524 Kb |
| Dokumentensprache | Englisch |
FEATURES. DESCRIPTIO. Sample Rate: 50Msps. 72.5dB SNR and 85dB SFDR (3.2V Range). 71dB SNR and 90dB SFDR (2V Range). APPLICATIO S
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LTC1743 12-Bit, 50Msps ADC
U FEATURES DESCRIPTIO
■
Sample Rate: 50Msps
The LTC®1743 is a 50Msps, sampling 12-bit A/D con- ■
72.5dB SNR and 85dB SFDR (3.2V Range)
verter designed for digitizing high frequency, wide ■
71dB SNR and 90dB SFDR (2V Range)
dynamic range signals. Pin selectable input ranges of ±1V ■ No Missing Codes and ±1.6V along with a resistor programmable mode ■ Single 5V Supply allow the LTC1743’s input range to be optimized for a ■ Power Dissipation: 1000mW wide variety of applications. ■ Selectable Input Ranges: ±1V or ±1.6V The LTC1743 is perfect for demanding communications ■ 150MHz Full Power Bandwidth S/H applications with AC performance that includes 72.5dB ■ Pin Compatible Family SNR and 85dB spurious free dynamic range. Ultralow jitter 25Msps: LTC1746 (14-Bit), LTC1745 (12-Bit) of 0.3ps 50Msps: LTC1744 (14-Bit), LTC1743 (12-Bit) RMS allows undersampling of IF frequencies with excellent noise performance. DC specs include ±1LSB 65Msps: LTC1742 (14-Bit), LTC1741 (12-Bit) maximum INL and ±0.8LSB DNL over temperature. 80Msps: LTC1748 (14-Bit), LTC1747 (12-Bit) ■ 48-Pin TSSOP Package The digital interface is compatible with 5V, 3V and 2V logic systems. The ENC and ENC inputs may be driven differen-
U
tially from PECL, GTL and other low swing logic families or
APPLICATIO S
from single-ended TTL or CMOS. The low noise, high gain ■ Telecommunications ENC and ENC inputs may also be driven by a sinusoidal ■ Receivers signal without degrading performance. A separate output ■ Cellular Base Stations power supply can be operated from 0.5V to 5V, making it ■ Spectrum Analysis easy to connect directly to any low voltage DSPs or FIFOs. ■ Imaging Systems The 48-pin TSSOP package with a flow-through pinout , LTC and LT are registered trademarks of Linear Technology Corporation. simplifies the board layout.
W BLOCK DIAGRA 50Msps, 12-Bit ADC with a 2V Differential Input Range
OVDD 0.5V TO 5V 0.1µF 0.1µF A + IN OF ±1V 12 D11 DIFFERENTIAL S/H 12-BIT OUTPUT • • ANALOG INPUT AMP PIPELINED ADC LATCHES • A – D0 IN CLKOUT SENSE OGND BUFFER VDD RANGE 5V SELECT 1µF 1µF 1µF DIFF AMP GND VCM 2.5VREF CONTROL LOGIC 4.7µF 1743 BD REFLB REFHA REFLA REFHB ENC ENC MSBINV OE 4.7µF 0.1µF 0.1µF DIFFERENTIAL ENCODE INPUT 1µF 1µF 1743f 1
U FEATURES DESCRIPTIO
■
Sample Rate: 50Msps
The LTC®1743 is a 50Msps, sampling 12-bit A/D con- ■
72.5dB SNR and 85dB SFDR (3.2V Range)
verter designed for digitizing high frequency, wide ■
71dB SNR and 90dB SFDR (2V Range)
dynamic range signals. Pin selectable input ranges of ±1V ■ No Missing Codes and ±1.6V along with a resistor programmable mode ■ Single 5V Supply allow the LTC1743’s input range to be optimized for a ■ Power Dissipation: 1000mW wide variety of applications. ■ Selectable Input Ranges: ±1V or ±1.6V The LTC1743 is perfect for demanding communications ■ 150MHz Full Power Bandwidth S/H applications with AC performance that includes 72.5dB ■ Pin Compatible Family SNR and 85dB spurious free dynamic range. Ultralow jitter 25Msps: LTC1746 (14-Bit), LTC1745 (12-Bit) of 0.3ps 50Msps: LTC1744 (14-Bit), LTC1743 (12-Bit) RMS allows undersampling of IF frequencies with excellent noise performance. DC specs include ±1LSB 65Msps: LTC1742 (14-Bit), LTC1741 (12-Bit) maximum INL and ±0.8LSB DNL over temperature. 80Msps: LTC1748 (14-Bit), LTC1747 (12-Bit) ■ 48-Pin TSSOP Package The digital interface is compatible with 5V, 3V and 2V logic systems. The ENC and ENC inputs may be driven differen-
U
tially from PECL, GTL and other low swing logic families or
APPLICATIO S
from single-ended TTL or CMOS. The low noise, high gain ■ Telecommunications ENC and ENC inputs may also be driven by a sinusoidal ■ Receivers signal without degrading performance. A separate output ■ Cellular Base Stations power supply can be operated from 0.5V to 5V, making it ■ Spectrum Analysis easy to connect directly to any low voltage DSPs or FIFOs. ■ Imaging Systems The 48-pin TSSOP package with a flow-through pinout , LTC and LT are registered trademarks of Linear Technology Corporation. simplifies the board layout.
W BLOCK DIAGRA 50Msps, 12-Bit ADC with a 2V Differential Input Range
OVDD 0.5V TO 5V 0.1µF 0.1µF A + IN OF ±1V 12 D11 DIFFERENTIAL S/H 12-BIT OUTPUT • • ANALOG INPUT AMP PIPELINED ADC LATCHES • A – D0 IN CLKOUT SENSE OGND BUFFER VDD RANGE 5V SELECT 1µF 1µF 1µF DIFF AMP GND VCM 2.5VREF CONTROL LOGIC 4.7µF 1743 BD REFLB REFHA REFLA REFHB ENC ENC MSBINV OE 4.7µF 0.1µF 0.1µF DIFFERENTIAL ENCODE INPUT 1µF 1µF 1743f 1