Datasheet LTC1742 (Analog Devices)
| Hersteller | Analog Devices |
| Beschreibung | 14-Bit, 65Msps Low Noise ADC |
| Seiten / Seite | 20 / 1 — FEATURES. DESCRIPTIO. Sample Rate: 65Msps. 76.5dB SNR and 90dB SFDR (3.2V … |
| Dateiformat / Größe | PDF / 586 Kb |
| Dokumentensprache | Englisch |
FEATURES. DESCRIPTIO. Sample Rate: 65Msps. 76.5dB SNR and 90dB SFDR (3.2V Range). 72.8dB SNR and 90dB SFDR (2V Range)
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LTC1742 14-Bit, 65Msps Low Noise ADC
U FEATURES DESCRIPTIO
■
Sample Rate: 65Msps
The LTC®1742 is an 65Msps, sampling 14-bit A/D con- ■
76.5dB SNR and 90dB SFDR (3.2V Range)
verter designed for digitizing high frequency, wide dy- ■
72.8dB SNR and 90dB SFDR (2V Range)
namic range signals. Pin selectable input ranges of ±1V ■ No Missing Codes and ±1.6V along with a resistor programmable mode ■ Single 5V Supply allow the LTC1742’s input range to be optimized for a wide ■ Power Dissipation: 1.275W variety of applications. ■ Selectable Input Ranges: ±1V or ±1.6V The LTC1742 is perfect for demanding communications ■ 240MHz Full Power Bandwidth S/H applications with AC performance that includes 76.5dB ■ Pin Compatible Family SNR and 90dB spurious free dynamic range. Ultralow jitter 25Msps: LTC1746 (14-Bit), LTC1745 (12-Bit) of 0.15ps 50Msps: LTC1744 (14-Bit), LTC1743 (12-Bit) RMS allows undersampling of IF frequencies with excellent noise performance. DC specs include ±3LSB INL 65Msps: LTC1742 (14-Bit), LTC1741 (12-Bit) and ±1LSB DNL. 80Msps: LTC1748 (14-Bit), LTC1747 (12-Bit) ■ 48-Pin TSSOP Package The digital interface is compatible with 5V, 3V, 2V and LVDS logic levels. The ENC and ENC inputs may be driven
U
differentially from PECL, GTL and other low swing logic
APPLICATIO S
families or from single-ended TTL or CMOS. The low ■ Telecommunications noise, high gain ENC and ENC inputs may also be driven ■ Receivers by a sinusoidal signal without degrading performance. A ■ Cellular Base Stations separate output power supply can be operated from 0.5V ■ Spectrum Analysis to 5V, making it easy to connect directly to low voltage ■ Imaging Systems DSPs or FIFOs. , LTC and LT are registered trademarks of Linear Technology Corporation. The TSSOP package with a flow-through pinout simplifies the board layout.
W BLOCK DIAGRA 65Msps, 14-Bit ADC with a 2V Differential Input Range
OVDD 0.5V TO 5V 0.1µF 0.1µF A + IN OF ±1V CORRECTION 14 D13 DIFFERENTIAL S/H 14-BIT LOGIC AND OUTPUT • • ANALOG INPUT AMP PIPELINED ADC SHIFT LATCHES • A – D0 IN REGISTER CLKOUT OGND SENSE BUFFER VDD 5V RANGE 1µF 1µF SELECT DIFF AMP 1µF VCM GND 2.35VREF CONTROL LOGIC 4.7µF 1742 BD REFLB REFHA REFLA REFHB ENC ENC MSBINV OE 4.7µF 0.1µF 0.1µF DIFFERENTIAL 1µF 1µF ENCODE INPUT 1742f 1
U FEATURES DESCRIPTIO
■
Sample Rate: 65Msps
The LTC®1742 is an 65Msps, sampling 14-bit A/D con- ■
76.5dB SNR and 90dB SFDR (3.2V Range)
verter designed for digitizing high frequency, wide dy- ■
72.8dB SNR and 90dB SFDR (2V Range)
namic range signals. Pin selectable input ranges of ±1V ■ No Missing Codes and ±1.6V along with a resistor programmable mode ■ Single 5V Supply allow the LTC1742’s input range to be optimized for a wide ■ Power Dissipation: 1.275W variety of applications. ■ Selectable Input Ranges: ±1V or ±1.6V The LTC1742 is perfect for demanding communications ■ 240MHz Full Power Bandwidth S/H applications with AC performance that includes 76.5dB ■ Pin Compatible Family SNR and 90dB spurious free dynamic range. Ultralow jitter 25Msps: LTC1746 (14-Bit), LTC1745 (12-Bit) of 0.15ps 50Msps: LTC1744 (14-Bit), LTC1743 (12-Bit) RMS allows undersampling of IF frequencies with excellent noise performance. DC specs include ±3LSB INL 65Msps: LTC1742 (14-Bit), LTC1741 (12-Bit) and ±1LSB DNL. 80Msps: LTC1748 (14-Bit), LTC1747 (12-Bit) ■ 48-Pin TSSOP Package The digital interface is compatible with 5V, 3V, 2V and LVDS logic levels. The ENC and ENC inputs may be driven
U
differentially from PECL, GTL and other low swing logic
APPLICATIO S
families or from single-ended TTL or CMOS. The low ■ Telecommunications noise, high gain ENC and ENC inputs may also be driven ■ Receivers by a sinusoidal signal without degrading performance. A ■ Cellular Base Stations separate output power supply can be operated from 0.5V ■ Spectrum Analysis to 5V, making it easy to connect directly to low voltage ■ Imaging Systems DSPs or FIFOs. , LTC and LT are registered trademarks of Linear Technology Corporation. The TSSOP package with a flow-through pinout simplifies the board layout.
W BLOCK DIAGRA 65Msps, 14-Bit ADC with a 2V Differential Input Range
OVDD 0.5V TO 5V 0.1µF 0.1µF A + IN OF ±1V CORRECTION 14 D13 DIFFERENTIAL S/H 14-BIT LOGIC AND OUTPUT • • ANALOG INPUT AMP PIPELINED ADC SHIFT LATCHES • A – D0 IN REGISTER CLKOUT OGND SENSE BUFFER VDD 5V RANGE 1µF 1µF SELECT DIFF AMP 1µF VCM GND 2.35VREF CONTROL LOGIC 4.7µF 1742 BD REFLB REFHA REFLA REFHB ENC ENC MSBINV OE 4.7µF 0.1µF 0.1µF DIFFERENTIAL 1µF 1µF ENCODE INPUT 1742f 1