Datasheet LTC1608 (Analog Devices) - 9
| Hersteller | Analog Devices |
| Beschreibung | High Speed, 16-Bit, 500ksps Sampling A/D Converter with Shutdown |
| Seiten / Seite | 20 / 9 — APPLICATIO S I FOR ATIO. Figure 3. CS top CONVST Setup Timing. Figure 4. … |
| Dateiformat / Größe | PDF / 816 Kb |
| Dokumentensprache | Englisch |
APPLICATIO S I FOR ATIO. Figure 3. CS top CONVST Setup Timing. Figure 4. Change in DNL vs CONVST Low Time. Be Sure the
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LTC1608
U U W U APPLICATIO S I FOR ATIO
(e.g., CONVST low time >t CS CONV), accuracy is unaffected. For best results, keep t5 less than 500ns or greater than t2 tCONV. CONVST Figures 5 through 9 show several different modes of t1 operation. In modes 1a and 1b (Figures 5 and 6), CS and RD RD are both tied low. The falling edge of CONVST starts the 1608 F03 conversion. The data outputs are always enabled and data can be latched with the BUSY rising edge. Mode 1a shows
Figure 3. CS top CONVST Setup Timing
operation with a narrow logic low CONVST pulse. Mode 1b shows a narrow logic high CONVST pulse. 4 In mode 2 (Figure 7) CS is tied low. The falling edge of CONVST signal starts the conversion. Data outputs are in 3 three-state until read by the MPU with the RD signal. Mode 2 can be used for operation with a shared data bus. 2 tCONV tACQ In slow memory and ROM modes (Figures 8 and 9), CS is tied low and CONVST and RD are tied together. The MPU CHANGE IN DNL (LSB) 1 starts the conversion and reads the output with the com- bined CONVST-RD signal. Conversions are started by the 0 MPU or DSP (no external sample clock is needed). 0 250 500 750 1000 1250 1500 1750 2000 CONVST LOW TIME, t5 (ns) In slow memory mode, the processor applies a logic low 1608 F04 to RD (= CONVST), starting the conversion. BUSY goes
Figure 4. Change in DNL vs CONVST Low Time. Be Sure the
low, forcing the processor into a wait state. The previous
CONVST Pulse Returns High Early in the Conversion or After the End of Conversion
conversion result appears on the data outputs. When the conversion is complete, the new conversion results
Timing and Control
appear on the data outputs; BUSY goes high, releasing the processor and the processor takes RD (= CONVST) back Conversion start and data read operations are controlled high and reads the new conversion data. by three digital inputs: CONVST, CS and RD. A falling edge applied to the CONVST pin will start a conversion after the In ROM mode, the processor takes RD (= CONVST) low, ADC has been selected (i.e., CS is low). Once initiated, it starting a conversion and reading the previous conversion cannot be restarted until the conversion is complete. result. After the conversion is complete, the processor can Converter status is indicated by the BUSY output. BUSY is read the new result and initiate another conversion. low during a conversion.
DIFFERENTIAL ANALOG INPUTS
We recommend using a narrow logic low or narrow logic high CONVST pulse to start a conversion as shown in
Driving the Analog Inputs
Figures 5 and 6. A narrow low or high CONVST pulse The differential analog inputs of the LTC1608 are easy to prevents the rising edge of the CONVST pulse from upset- drive. The inputs may be driven differentially or as a single- ting the critical bit decisions during the conversion time. ended input (i.e., the A – input is grounded). The A + and Figure 4 shows the change of the differential nonlinearity IN IN A – inputs are sampled at the same instant. Any un- error versus the low time of the CONVST pulse. As shown, IN wanted signal that is common mode to both inputs will be if CONVST returns high early in the conversion (e.g., reduced by the common mode rejection of the sample- CONVST low time <300ns), accuracy is unaffected. Simi- and-hold circuit. The inputs draw only one small current larly, if CONVST returns high after the conversion is over 9
U U W U APPLICATIO S I FOR ATIO
(e.g., CONVST low time >t CS CONV), accuracy is unaffected. For best results, keep t5 less than 500ns or greater than t2 tCONV. CONVST Figures 5 through 9 show several different modes of t1 operation. In modes 1a and 1b (Figures 5 and 6), CS and RD RD are both tied low. The falling edge of CONVST starts the 1608 F03 conversion. The data outputs are always enabled and data can be latched with the BUSY rising edge. Mode 1a shows
Figure 3. CS top CONVST Setup Timing
operation with a narrow logic low CONVST pulse. Mode 1b shows a narrow logic high CONVST pulse. 4 In mode 2 (Figure 7) CS is tied low. The falling edge of CONVST signal starts the conversion. Data outputs are in 3 three-state until read by the MPU with the RD signal. Mode 2 can be used for operation with a shared data bus. 2 tCONV tACQ In slow memory and ROM modes (Figures 8 and 9), CS is tied low and CONVST and RD are tied together. The MPU CHANGE IN DNL (LSB) 1 starts the conversion and reads the output with the com- bined CONVST-RD signal. Conversions are started by the 0 MPU or DSP (no external sample clock is needed). 0 250 500 750 1000 1250 1500 1750 2000 CONVST LOW TIME, t5 (ns) In slow memory mode, the processor applies a logic low 1608 F04 to RD (= CONVST), starting the conversion. BUSY goes
Figure 4. Change in DNL vs CONVST Low Time. Be Sure the
low, forcing the processor into a wait state. The previous
CONVST Pulse Returns High Early in the Conversion or After the End of Conversion
conversion result appears on the data outputs. When the conversion is complete, the new conversion results
Timing and Control
appear on the data outputs; BUSY goes high, releasing the processor and the processor takes RD (= CONVST) back Conversion start and data read operations are controlled high and reads the new conversion data. by three digital inputs: CONVST, CS and RD. A falling edge applied to the CONVST pin will start a conversion after the In ROM mode, the processor takes RD (= CONVST) low, ADC has been selected (i.e., CS is low). Once initiated, it starting a conversion and reading the previous conversion cannot be restarted until the conversion is complete. result. After the conversion is complete, the processor can Converter status is indicated by the BUSY output. BUSY is read the new result and initiate another conversion. low during a conversion.
DIFFERENTIAL ANALOG INPUTS
We recommend using a narrow logic low or narrow logic high CONVST pulse to start a conversion as shown in
Driving the Analog Inputs
Figures 5 and 6. A narrow low or high CONVST pulse The differential analog inputs of the LTC1608 are easy to prevents the rising edge of the CONVST pulse from upset- drive. The inputs may be driven differentially or as a single- ting the critical bit decisions during the conversion time. ended input (i.e., the A – input is grounded). The A + and Figure 4 shows the change of the differential nonlinearity IN IN A – inputs are sampled at the same instant. Any un- error versus the low time of the CONVST pulse. As shown, IN wanted signal that is common mode to both inputs will be if CONVST returns high early in the conversion (e.g., reduced by the common mode rejection of the sample- CONVST low time <300ns), accuracy is unaffected. Simi- and-hold circuit. The inputs draw only one small current larly, if CONVST returns high after the conversion is over 9