Datasheet LTC1605-1, LTC1605-2 (Analog Devices) - 7
| Hersteller | Analog Devices |
| Beschreibung | Single Supply 16-Bit, 100ksps, Sampling ADCs |
| Seiten / Seite | 22 / 7 — pin FuncTions VIN (Pin 1):. AGND1 (Pin 2):. R/C (Pin 24):. REF (Pin 3):. … |
| Dateiformat / Größe | PDF / 405 Kb |
| Dokumentensprache | Englisch |
pin FuncTions VIN (Pin 1):. AGND1 (Pin 2):. R/C (Pin 24):. REF (Pin 3):. CAP (Pin 4):. CS (Pin 25):. AGND2 (Pin 5):. BUSY (Pin 26):
Modelllinie für dieses Datenblatt
Textversion des Dokuments
LTC1605-1/LTC1605-2
pin FuncTions VIN (Pin 1):
Analog Input. Connect through a 200Ω being the LSB. With BYTE high the upper eight bits and resistor to the analog input. Full-scale input range is 0V the lower eight bits will be switched. The MSB is output to 4V for the LTC1605-1 and ±4V for the LTC1605-2. on Pin 15 and bit 8 is output on Pin 22. Bit 7 is output on
AGND1 (Pin 2):
Analog Ground. Tie to analog ground Pin 6 and the LSB is output on Pin 13. plane.
R/C (Pin 24):
Read/Convert Input. With CS low, a falling
REF (Pin 3):
2.5V Reference Output. Bypass with 2.2µF edge on R/C puts the internal sample-and-hold into the tantalum capacitor. Can be driven with an external refer- hold state and starts a conversion. With CS low, a rising ence. edge on R/C enables the output data bits.
CAP (Pin 4):
Reference Buffer Output. Bypass with 2.2µF
CS (Pin 25):
Chip Select. Internally OR’d with R/C. With tantalum capacitor. R/C low, a falling edge on CS will initiate a conversion. With R/C high, a falling edge on CS will enable the output data.
AGND2 (Pin 5):
Analog Ground. Tie to analog ground plane.
BUSY (Pin 26):
Output Shows Converter Status. It is low
D15 to D8 (Pins 6 to 13):
Three-State Data Outputs. when a conversion is in progress. Data valid on the rising Hi-Z state when CS is high or when R/C is low. edge of BUSY. CS or R/C must be high when BUSY rises
DGND (Pin 14):
Digital Ground. or another conversion will start without time for signal acquisition.
D7 to D0 (Pins 15 to 22):
Three-State Data Outputs. Hi-Z state when CS is high or when R/C is low.
VANA (Pin 27):
5V Analog Supply. Bypass to ground with a 0.1µF ceramic and a 10µF tantalum capacitor.
BYTE (Pin 23):
Byte Select. With BYTE low, data will be output with Pin 6 (D15) being the MSB and Pin 22 (D0)
VDIG (Pin 28):
5V Digital Supply. Connect directly to Pin 27.
FuncTional block DiagraM
4k CSAMPLE 6K* VIN 10k 20k VANA OPEN* 3.75k* CSAMPLE VDIG ZEROING SWITCHES 4k REF 2.5V REF + REF BUF 16-BIT CAPACITIVE DAC COMP – CAP (2.5V) 16 SUCCESSIVE APPROXIMATION • D15 • REGISTER OUTPUT LATCHES • D0 AGND1 AGND2 INTERNAL DGND CONTROL LOGIC CLOCK 1605-1/2 BD *RESISTOR VALUES FOR THE LTC1605-2 CS R/C BYTE BUSY 160512fa For more information www.linear.com/LTC1605-1 7
pin FuncTions VIN (Pin 1):
Analog Input. Connect through a 200Ω being the LSB. With BYTE high the upper eight bits and resistor to the analog input. Full-scale input range is 0V the lower eight bits will be switched. The MSB is output to 4V for the LTC1605-1 and ±4V for the LTC1605-2. on Pin 15 and bit 8 is output on Pin 22. Bit 7 is output on
AGND1 (Pin 2):
Analog Ground. Tie to analog ground Pin 6 and the LSB is output on Pin 13. plane.
R/C (Pin 24):
Read/Convert Input. With CS low, a falling
REF (Pin 3):
2.5V Reference Output. Bypass with 2.2µF edge on R/C puts the internal sample-and-hold into the tantalum capacitor. Can be driven with an external refer- hold state and starts a conversion. With CS low, a rising ence. edge on R/C enables the output data bits.
CAP (Pin 4):
Reference Buffer Output. Bypass with 2.2µF
CS (Pin 25):
Chip Select. Internally OR’d with R/C. With tantalum capacitor. R/C low, a falling edge on CS will initiate a conversion. With R/C high, a falling edge on CS will enable the output data.
AGND2 (Pin 5):
Analog Ground. Tie to analog ground plane.
BUSY (Pin 26):
Output Shows Converter Status. It is low
D15 to D8 (Pins 6 to 13):
Three-State Data Outputs. when a conversion is in progress. Data valid on the rising Hi-Z state when CS is high or when R/C is low. edge of BUSY. CS or R/C must be high when BUSY rises
DGND (Pin 14):
Digital Ground. or another conversion will start without time for signal acquisition.
D7 to D0 (Pins 15 to 22):
Three-State Data Outputs. Hi-Z state when CS is high or when R/C is low.
VANA (Pin 27):
5V Analog Supply. Bypass to ground with a 0.1µF ceramic and a 10µF tantalum capacitor.
BYTE (Pin 23):
Byte Select. With BYTE low, data will be output with Pin 6 (D15) being the MSB and Pin 22 (D0)
VDIG (Pin 28):
5V Digital Supply. Connect directly to Pin 27.
FuncTional block DiagraM
4k CSAMPLE 6K* VIN 10k 20k VANA OPEN* 3.75k* CSAMPLE VDIG ZEROING SWITCHES 4k REF 2.5V REF + REF BUF 16-BIT CAPACITIVE DAC COMP – CAP (2.5V) 16 SUCCESSIVE APPROXIMATION • D15 • REGISTER OUTPUT LATCHES • D0 AGND1 AGND2 INTERNAL DGND CONTROL LOGIC CLOCK 1605-1/2 BD *RESISTOR VALUES FOR THE LTC1605-2 CS R/C BYTE BUSY 160512fa For more information www.linear.com/LTC1605-1 7