Datasheet LTC1603 (Analog Devices) - 8

LTC1603
U U W U APPLICATIONS INFORMATION CONVERSION DETAILS
summing junctions. This input charge is successively compared with the binary-weighted charges supplied by The LTC1603 uses a successive approximation algorithm the differential capacitive DAC. Bit decisions are made by and internal sample-and-hold circuit to convert an analog the high speed comparator. At the end of a conversion, the signal to a 16-bit parallel output. The ADC is complete with differential DAC output balances the A + and A – input a sample-and-hold, a precision reference and an internal IN IN charges. The SAR contents (a 16-bit data word) which clock. The control logic provides easy interface to micro- represent the difference of A + and A – are loaded into processors and DSPs. (Please refer to the Digital Interface IN IN the 16-bit output latches. section for the data format.) Conversion start is controlled by the CS and CONVST
DIGITAL INTERFACE
inputs. At the start of the conversion the successive The A/D converter is designed to interface with micropro- approximation register (SAR) resets. Once a conversion cessors as a memory mapped device. The CS and RD cycle has begun it cannot be restarted. control inputs are common to all peripheral memory During the conversion, the internal differential 16-bit interfacing. A separate CONVST is used to initiate a con- capacitive DAC output is sequenced by the SAR from the version. Most Significant Bit (MSB) to the Least Significant Bit (LSB). Referring to Figure 1, the A + –
Internal Clock
IN and AIN inputs are acquired during the acquire phase and the comparator The A/D converter has an internal clock that runs the A/D offset is nulled by the zeroing switches. In this acquire conversion. The internal clock is factory trimmed to achieve phase, a duration of 480ns will provide enough time for the a typical conversion time of 3.3µs and a maximum conver- sample-and-hold capacitors to acquire the analog signal. sion time of 3.8µs over the full temperature range. No During the convert phase the comparator zeroing switches external adjustments are required. The guaranteed maxi- open, putting the comparator into compare mode. The mum acquisition time is 480ns. In addition, a throughput input switches connect the CSMPL capacitors to ground, time (acquisition + conversion) of 4µs and a minimum transferring the differential analog input charge onto the sampling rate of 250ksps are guaranteed.
3V Input/Output Compatible
CSMPL SAMPLE A + The LTC1603 operates on IN ±5V supplies, which makes the HOLD device easy to interface to 5V digital systems. This device can also talk to 3V digital systems: the digital input pins ZEROING SWITCHES CSMPL HOLD (SHDN, CS, CONVST and RD) of the LTC1603 recognize SAMPLE A – IN 3V or 5V inputs. The LTC1603 has a dedicated output HOLD HOLD supply pin (OVDD) that controls the output swings of the +C digital output pins (D0 to D15, BUSY) and allows the part DAC + to talk to either 3V or 5V digital systems. The output is –CDAC COMP two’s complement binary. – +VDAC
Power Shutdown
–VDAC The LTC1603 provides two power shutdown modes, Nap 16 D15 OUTPUT • • and Sleep, to save power during inactive periods. The Nap SAR LATCHES • D0 mode reduces the power by 95% and leaves only the 1603 F01 digital logic and reference powered up. The wake-up time from Nap to active is 200ns. In Sleep mode all bias
Figure 1. Simplified Block Diagram
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