Datasheet LTC1417 (Analog Devices) - 5

HerstellerAnalog Devices
BeschreibungLow Power 14-Bit, 400ksps Sampling ADC Converter with Serial I/O
Seiten / Seite32 / 5 — W U. TI I G CHARACTERISTICS The
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DokumentenspracheEnglisch

W U. TI I G CHARACTERISTICS The

W U TI I G CHARACTERISTICS The

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LTC1417
W U TI I G CHARACTERISTICS The

indicates specifications which apply over the full operating temperature range, otherwise specifications are at TA = 25
°
C. (Note 5) SYMBOL PARAMETER CONDITIONS MIN TYP MAX UNITS
tH SCLK SCLK High Time (Note 9) ● 10 ns tL SCLK SCLK Low Time (Note 9) ● 10 ns tH EXTCLKIN EXTCLKIN High Time ● 0.04 20 µs tL EXTCLKIN EXTCLKIN Low Time ● 0.04 20 µs fCLKOUT Conversion Clock Output Frequency Internal Conversion 9.4 MHz Clock Mode (EXTCLKIN = 5V) External Conversion Clock Mode fEXTCLKIN MHz (EXTCLKIN is Driven by an External Conversion Clock Input)
Note 1:
Absolute Maximum Ratings are those values beyond which the life
Note 7:
Integral nonlinearity is defined as the deviation of a code from a of a device may be impaired. straight line passing through the actual endpoints of the transfer curve.
Note 2:
All voltage values are with respect to ground with DGND and The deviation is measured from the center of the quantization band. AGND wired together (unless otherwise noted).
Note 8:
Bipolar offset is the offset voltage measured from – 0.5LSB
Note 3:
When these pin voltages are taken below V when the output code flickers between 0000 0000 0000 00 and SS or above VDD, they will be clamped by internal diodes. This product can handle input currents 1111 1111 1111 11. greater than 100mA without latchup if the pin is driven below VSS (ground
Note 9:
Guaranteed by design, not subject to test. for unipolar mode) or above VDD.
Note 10:
Recommended operating conditions.
Note 4:
When these pin voltages are taken below VSS they will be clamped
Note 11:
The falling CONVST edge starts a conversion. If CONVST returns by internal diodes. This product can handle input currents greater than high at a critical point during the conversion it can create small errors. For 100mA below VSS without latchup. These pins are not clamped to VDD. best results ensure that CONVST returns high either within 625ns after
Note 5:
VDD = 5V, VSS = – 5V, fSAMPLE = 400kHz, tr = tf = 5ns unless conversion start or after BUSY rises. otherwise specified.
Note 12:
Typical RMS noise at the code transitions. See Figure 2 for
Note 6:
Linearity, offset and full-scale specifications apply for a single- histogram. ended A + – IN input with AIN grounded.
Note 13:
t11 of 40ns maximum allows fSCLK up to 10MHz for rising capture with 50% duty cycle. fSCLK up to 20MHz for falling capture with 5ns setup time.
W U TYPICAL PERFOR A CE CHARACTERISTICS (TA = 25
°
C, unless otherwise specified) Differential Nonlinearity S/(N + D) vs Input Frequency Typical INL Curve vs Output Code and Amplitude
1.0 1.0 90 80 VIN = 0dB 70 0.5 0.5 60 VIN = –20dB 50 0 0 40 INL (LSBs) 30 DNL ERROR (LSBs) VIN = –60dB –0.5 – 0.5 20 SIGNAL/(NOISE + DISTORTION) (dB) 10 –1.0 –1.0 0 0 4096 8192 12288 16384 0 4096 8192 12288 16384 1k 10k 100k 1M OUTPUT CODE OUTPUT CODE INPUT FREQUENCY (Hz) 1417 G02 1417 G03 1417 G01 sn1417 1417fas 5