Datasheet LTC1416 (Analog Devices) - 7
| Hersteller | Analog Devices |
| Beschreibung | Low Power 14-Bit, 400ksps Sampling ADC |
| Seiten / Seite | 20 / 7 — TEST CIRCUITS. Load Circuits for Access Timing. Load Circuits for Output … |
| Dateiformat / Größe | PDF / 338 Kb |
| Dokumentensprache | Englisch |
TEST CIRCUITS. Load Circuits for Access Timing. Load Circuits for Output Float Delay. APPLICATIONS INFORMATION
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LTC1416
TEST CIRCUITS Load Circuits for Access Timing Load Circuits for Output Float Delay
5V 5V 1k 1k DBN DBN DBN DBN 1k CL CL 1k 100pF 100pF (A) Hi-Z TO VOH AND VOL TO VOH (B) Hi-Z TO VOL AND VOH TO VOL (A) VOH TO Hi-Z (B) VOL TO Hi-Z 1416 TC01 1416 TC02
U U W U APPLICATIONS INFORMATION CONVERSION DETAILS
Conversion start is controlled by the CS and CONVST inputs. At the start of the conversion, the successive The LTC1416 uses a successive approximation algorithm approximation register (SAR) is reset. Once a conversion and an internal sample-and-hold circuit to convert an cycle has begun, it cannot be restarted. analog signal to a 14-bit parallel output. The ADC is complete with a precision reference and an internal clock. During the conversion, the internal differential 14-bit The control logic provides easy interface to microproces- capacitive DAC output is sequenced by the SAR from the sors and DSPs. (Please refer to the Digital Interface most significant bit (MSB) to the least significant bit section for the data format.) (LSB). Referring to Figure 1, the A + – IN and AIN inputs are connected to the sample-and-hold capacitors (CSAMPLE) during the acquire phase and the comparator offset is C + SAMPLE SAMPLE A + nulled by the zeroing switches. In this acquire phase, a IN HOLD minimum delay of 400ns will provide enough time for the C – SAMPLE SAMPLE HOLD sample-and-hold capacitors to acquire the analog signal. A – IN During the convert phase the comparator zeroing switches HOLD ZEROING SWITCHES open, putting the comparator into compare mode. The C + DAC HOLD input switches connect the CSAMPLE capacitors to ground, + transferring the differential analog input charge onto the V + DAC C – DAC COMP summing junction. This input charge is successively com- – pared with the binary-weighted charges supplied by the differential capacitive DAC. Bit decisions are made by the V – DAC 14 OUTPUT • D13 high speed comparator. At the end of a conversion, the SAR • LATCH • D0 differential DAC output balances the A + – IN and AIN input 1416 F01 charges. The SAR contents (a 14-bit data word) which represents the difference of A + – IN and AIN are loaded into
Figure 1. Simplified Block Diagram
the 14-bit output latches. 7
TEST CIRCUITS Load Circuits for Access Timing Load Circuits for Output Float Delay
5V 5V 1k 1k DBN DBN DBN DBN 1k CL CL 1k 100pF 100pF (A) Hi-Z TO VOH AND VOL TO VOH (B) Hi-Z TO VOL AND VOH TO VOL (A) VOH TO Hi-Z (B) VOL TO Hi-Z 1416 TC01 1416 TC02
U U W U APPLICATIONS INFORMATION CONVERSION DETAILS
Conversion start is controlled by the CS and CONVST inputs. At the start of the conversion, the successive The LTC1416 uses a successive approximation algorithm approximation register (SAR) is reset. Once a conversion and an internal sample-and-hold circuit to convert an cycle has begun, it cannot be restarted. analog signal to a 14-bit parallel output. The ADC is complete with a precision reference and an internal clock. During the conversion, the internal differential 14-bit The control logic provides easy interface to microproces- capacitive DAC output is sequenced by the SAR from the sors and DSPs. (Please refer to the Digital Interface most significant bit (MSB) to the least significant bit section for the data format.) (LSB). Referring to Figure 1, the A + – IN and AIN inputs are connected to the sample-and-hold capacitors (CSAMPLE) during the acquire phase and the comparator offset is C + SAMPLE SAMPLE A + nulled by the zeroing switches. In this acquire phase, a IN HOLD minimum delay of 400ns will provide enough time for the C – SAMPLE SAMPLE HOLD sample-and-hold capacitors to acquire the analog signal. A – IN During the convert phase the comparator zeroing switches HOLD ZEROING SWITCHES open, putting the comparator into compare mode. The C + DAC HOLD input switches connect the CSAMPLE capacitors to ground, + transferring the differential analog input charge onto the V + DAC C – DAC COMP summing junction. This input charge is successively com- – pared with the binary-weighted charges supplied by the differential capacitive DAC. Bit decisions are made by the V – DAC 14 OUTPUT • D13 high speed comparator. At the end of a conversion, the SAR • LATCH • D0 differential DAC output balances the A + – IN and AIN input 1416 F01 charges. The SAR contents (a 14-bit data word) which represents the difference of A + – IN and AIN are loaded into
Figure 1. Simplified Block Diagram
the 14-bit output latches. 7