Datasheet LTC1410 (Analog Devices) - 6
| Hersteller | Analog Devices |
| Beschreibung | 12-Bit, 1.25Msps, Sampling A/D Converter with Shutdown |
| Seiten / Seite | 16 / 6 — PI FU CTIO S. + AIN (Pin 1):. SHDN (Pin 21):. – A. IN (Pin 2):. VREF (Pin … |
| Dateiformat / Größe | PDF / 162 Kb |
| Dokumentensprache | Englisch |
PI FU CTIO S. + AIN (Pin 1):. SHDN (Pin 21):. – A. IN (Pin 2):. VREF (Pin 3):. RD (Pin 22):. REFCOMP (Pin 4):. CONVST (Pin 23):
Modelllinie für dieses Datenblatt
Textversion des Dokuments
LTC1410
U U U PI FU CTIO S + AIN (Pin 1):
Positive Analog Input, ±2.5V.
SHDN (Pin 21):
Power Shutdown Input. A low logic
– A
level will invoke the Shutdown mode selected by the
IN (Pin 2):
Negative Analog Input, ±2.5V. NAP/SLP pin.
VREF (Pin 3):
2.50V Reference Output.
RD (Pin 22):
Read Input. This enables the output
REFCOMP (Pin 4):
4.06V Reference Bypass Pin. By- drivers when CS is low. pass to AGND with 10µF tantalum in parallel with 0.1µF ceramic.
CONVST (Pin 23):
Conversion Start Signal. This active low signal starts a conversion on its falling edge.
AGND (Pin 5):
Analog Ground.
CS (Pin 24):
The Chip Select input must be low for the
D11 to D4 (Pins 6 to 13):
Three-State Data Outputs. ADC to recognize CONVST and RD inputs.
DGND (Pin 14):
Digital Ground for Internal Logic. Tie to
BUSY (Pin 25):
The BUSY output shows the converter AGND. status. It is low when a conversion is in progress. Data
D3 to D0 (Pins 15 to 18):
Three-State Data Outputs. valid on the rising edge of BUSY.
OGND (Pin 19):
Digital Ground for Output Drivers. Tie
VSS (Pin 26):
–5V Negative Supply. Bypass to AGND to AGND. with 10µF tantalum in parallel 0.1µF ceramic.
NAP/SLP (Pin 20):
Power Shutdown Mode. Selects the
DVDD (Pin 27):
5V Positive Supply. Short to Pin 28. mode invoked by the SHDN pin. Low selects Sleep
AV
mode and high selects quick wake-up Nap mode.
DD (Pin 28):
5V Positive Supply. Bypass to AGND with 10µF tantalum in parallel with 0.1µF ceramic.
U U W FU CTIO AL BLOCK DIAGRA
CSAMPLE +AIN AVDD CSAMPLE – AIN DVDD 2k ZEROING SWITCHES VREF 2.5V REF VSS + REF AMP 12-BIT CAPACITIVE DAC COMP – REFCOMP (4V) 12 SUCCESSIVE APPROXIMATION • D11 OUTPUT LATCHES • REGISTER • D0 AGND INTERNAL CONTROL LOGIC DGND CLOCK NAP/SLP SHDN CONVST RD CS BUSY LTC1410 • BD 6
U U U PI FU CTIO S + AIN (Pin 1):
Positive Analog Input, ±2.5V.
SHDN (Pin 21):
Power Shutdown Input. A low logic
– A
level will invoke the Shutdown mode selected by the
IN (Pin 2):
Negative Analog Input, ±2.5V. NAP/SLP pin.
VREF (Pin 3):
2.50V Reference Output.
RD (Pin 22):
Read Input. This enables the output
REFCOMP (Pin 4):
4.06V Reference Bypass Pin. By- drivers when CS is low. pass to AGND with 10µF tantalum in parallel with 0.1µF ceramic.
CONVST (Pin 23):
Conversion Start Signal. This active low signal starts a conversion on its falling edge.
AGND (Pin 5):
Analog Ground.
CS (Pin 24):
The Chip Select input must be low for the
D11 to D4 (Pins 6 to 13):
Three-State Data Outputs. ADC to recognize CONVST and RD inputs.
DGND (Pin 14):
Digital Ground for Internal Logic. Tie to
BUSY (Pin 25):
The BUSY output shows the converter AGND. status. It is low when a conversion is in progress. Data
D3 to D0 (Pins 15 to 18):
Three-State Data Outputs. valid on the rising edge of BUSY.
OGND (Pin 19):
Digital Ground for Output Drivers. Tie
VSS (Pin 26):
–5V Negative Supply. Bypass to AGND to AGND. with 10µF tantalum in parallel 0.1µF ceramic.
NAP/SLP (Pin 20):
Power Shutdown Mode. Selects the
DVDD (Pin 27):
5V Positive Supply. Short to Pin 28. mode invoked by the SHDN pin. Low selects Sleep
AV
mode and high selects quick wake-up Nap mode.
DD (Pin 28):
5V Positive Supply. Bypass to AGND with 10µF tantalum in parallel with 0.1µF ceramic.
U U W FU CTIO AL BLOCK DIAGRA
CSAMPLE +AIN AVDD CSAMPLE – AIN DVDD 2k ZEROING SWITCHES VREF 2.5V REF VSS + REF AMP 12-BIT CAPACITIVE DAC COMP – REFCOMP (4V) 12 SUCCESSIVE APPROXIMATION • D11 OUTPUT LATCHES • REGISTER • D0 AGND INTERNAL CONTROL LOGIC DGND CLOCK NAP/SLP SHDN CONVST RD CS BUSY LTC1410 • BD 6