Datasheet LTC1408 (Analog Devices) - 9
| Hersteller | Analog Devices |
| Beschreibung | 6 Channel, 14-Bit, 600ksps Simultaneous Sampling ADC with Shutdown |
| Seiten / Seite | 20 / 9 — PI FU CTIO S. CONV (Pin 30):. SCK (Pin 32):. DGND (Pin 31):. EXPOSED PAD … |
| Dateiformat / Größe | PDF / 513 Kb |
| Dokumentensprache | Englisch |
PI FU CTIO S. CONV (Pin 30):. SCK (Pin 32):. DGND (Pin 31):. EXPOSED PAD (Pin 33):. BLOCK DIAGRA
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LTC1408
U U U PI FU CTIO S CONV (Pin 30):
Convert Start. Holds the six analog input
SCK (Pin 32):
External Clock Input. Advances the conver- signals and starts the conversion on the rising edge. Two sion process and sequences the output data at SD0 (Pin1) pulses with SCK in fixed high or fixed low state starts Nap on the rising edge. One or more pulses wake from sleep mode. Four or more pulses with SCK in fixed high or fixed or nap power saving modes. 16 clock cycles are needed low state starts Sleep mode. for each of the channels that are activated by SELx (Pins 26, 27, 28), up to a total of 96 clock cycles needed to
DGND (Pin 31):
Digital Ground. This ground pin must be convert and read out all 6 channels. tied directly to the solid ground plane. Digital input signal currents flow through this pin.
EXPOSED PAD (Pin 33):
GND. Must be tied directly to the solid ground plane.
W BLOCK DIAGRA
0.1µF 10µF 3V VCC VDD 24 25 LTC1408 CH0+ 4 + S & H CH0– 5 – 6 CH1+ 7 + S & H CH1– 8 – 9 CH2+ 10 + OVDD 3V S & H 14-BIT LATCH 0 3 CH2– 11 – 14-BIT LATCH 1 THREE- SD0 STATE 0.1µF 600ksps 14-BIT LATCH 2 MUX SERIAL 1 12 13 14-BIT ADC 14-BIT LATCH 3 OUTPUT OGND CH3+ 14-BIT LATCH 4 14 + PORT 2 14-BIT LATCH 5 S & H CH3– 15 – 16 TIMING 30 CONV CH4+ LOGIC 17 + S & H 32 SCK CH4– 18 – 19 CH5+ 20 + S & H CH5– 21 – 2.5V REFERENCE V EXPOSED PAD REF 33 22 23 29 26 27 28 31 GND 10µF DGND BIP SEL2 SEL1 SEL0 1408 BD 1408fa 9
U U U PI FU CTIO S CONV (Pin 30):
Convert Start. Holds the six analog input
SCK (Pin 32):
External Clock Input. Advances the conver- signals and starts the conversion on the rising edge. Two sion process and sequences the output data at SD0 (Pin1) pulses with SCK in fixed high or fixed low state starts Nap on the rising edge. One or more pulses wake from sleep mode. Four or more pulses with SCK in fixed high or fixed or nap power saving modes. 16 clock cycles are needed low state starts Sleep mode. for each of the channels that are activated by SELx (Pins 26, 27, 28), up to a total of 96 clock cycles needed to
DGND (Pin 31):
Digital Ground. This ground pin must be convert and read out all 6 channels. tied directly to the solid ground plane. Digital input signal currents flow through this pin.
EXPOSED PAD (Pin 33):
GND. Must be tied directly to the solid ground plane.
W BLOCK DIAGRA
0.1µF 10µF 3V VCC VDD 24 25 LTC1408 CH0+ 4 + S & H CH0– 5 – 6 CH1+ 7 + S & H CH1– 8 – 9 CH2+ 10 + OVDD 3V S & H 14-BIT LATCH 0 3 CH2– 11 – 14-BIT LATCH 1 THREE- SD0 STATE 0.1µF 600ksps 14-BIT LATCH 2 MUX SERIAL 1 12 13 14-BIT ADC 14-BIT LATCH 3 OUTPUT OGND CH3+ 14-BIT LATCH 4 14 + PORT 2 14-BIT LATCH 5 S & H CH3– 15 – 16 TIMING 30 CONV CH4+ LOGIC 17 + S & H 32 SCK CH4– 18 – 19 CH5+ 20 + S & H CH5– 21 – 2.5V REFERENCE V EXPOSED PAD REF 33 22 23 29 26 27 28 31 GND 10µF DGND BIP SEL2 SEL1 SEL0 1408 BD 1408fa 9