LTC1407-1/LTC1407A-1 Serial 12-Bit/14-Bit, 3Msps Simultaneous Sampling ADCs with Shutdown FEATURESDESCRIPTION n 3Msps Sampling ADC with Two Simultaneous The LTC®1407-1/LTC1407A-1 are 12-bit/14-bit, 3Msps Differential Inputs ADCs with two 1.5Msps simultaneously sampled differ- n 1.5Msps Throughput per Channel ential inputs. The devices draw only 4.7mA from a single n Low Power Dissipation: 14mW (Typ) 3V supply and come in a tiny 10-lead MS package. A sleep n 3V Single Supply Operation shutdown feature lowers power consumption to 10μW. n ±1.25V Differential Input Range The combination of speed, low power and tiny package n Pin Compatible 0V to 2.5V Input Range Version makes the LTC1407-1/LTC1407A-1 suitable for high speed, (LTC1407/LTC1407A) portable applications. n 2.5V Internal Bandgap Reference with External The LTC1407-1/LTC1407A-1 contain two separate differ- Overdrive ential inputs that are sampled simultaneously on the rising n 3-Wire Serial Interface edge of the CONV signal. These two sampled inputs are n Sleep (10μW) Shutdown Mode then converted at a rate of 1.5Msps per channel. n Nap (3mW) Shutdown Mode n 80dB Common Mode Rejection at 100kHz The 80dB common mode rejection allows users to eliminate n Tiny 10-Lead MS Package ground loops and common mode noise by measuring signals differentially from the source. The devices convert –1.25V to 1.25V bipolar inputs differ- APPLICATIONS entially. The absolute voltage swing for CH0+, CH0–, CH1+ n Telecommunications and CH1– extends from ground to the supply voltage. n Data Acquisition Systems The serial interface sends out the two conversion results in 32 n Uninterrupted Power Supplies clocks for compatibility with standard serial interfaces. n Multiphase Motor Control L, LT, LTC, LTM, Linear Technology and the Linear logo are registered trademarks of Linear n I & Q Demodulation Technology Corporation. All other trademarks are the property of their respective owners. n Protected by U.S. Patents including 6084440, 6522187. Industrial Radio BLOCK DIAGRAM 10μF 3V THD, 2nd and 3rd vs Input Frequencyfor Differential Input Signals 7 VDD LTC1407A-1 –44 CH0+ 1 + –50 TCH S & H –56 CH0– 2 – THREE- –62 14-BIT LA STATE 3Msps MUX SERIAL 8 SDO –68 14-BIT ADC OUTPUT –74 CH1+ TCH 4 + PORT THD –80 3RD S & H THD, 2ND, 3RD (dB) –86 CH1– 14-BIT LA 5 – 10 CONV –92 TIMING VREF LOGIC –98 3 2ND 9 SCK 10μF –104 GND 2.5V 0.1 1 10 20 6 REFERENCE FREQUENCY (MHz) 11 EXPOSED PAD 14071 TA01b 1407A1 BD 14071fb 1