Datasheet LTC1406 (Analog Devices) - 5
| Hersteller | Analog Devices |
| Beschreibung | Low Power, 8-Bit, 20Msps, Sampling A/D Converter |
| Seiten / Seite | 16 / 5 — TYPICAL PERFORMANCE CHARACTERISTICS. Spurious-Free Dynamic Range. … |
| Dateiformat / Größe | PDF / 381 Kb |
| Dokumentensprache | Englisch |
TYPICAL PERFORMANCE CHARACTERISTICS. Spurious-Free Dynamic Range. Differential Nonlinearity. vs Input Frequency
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LTC1406
W U TYPICAL PERFORMANCE CHARACTERISTICS Spurious-Free Dynamic Range Differential Nonlinearity vs Input Frequency Intermodulation Distortion Plot vs Output Code
70 0 1.0 f –10 SAMPLE = 20MHz 60 fIN1 = 3.500977MHz –20 fIN2 = 3.598633MHz 0.5 50 –30 40 –40 –50 0 30 –60 AMPLITUDE (dB) 20 –70 DNL EOC ERROR (LSB) –0.5 –80 10 SPURIOUS-FREE DYNAMIC RANGE (dB) –90 0 –100 –1.0 100k 1M 10M 100M 0 1 2 3 4 5 6 7 8 9 10 0 32 64 96 128 160 192 224 256 INPUT FREQUENCY (Hz) FREQUENCY (MHz) OUTPUT CODE 1406 G04 1406 G05 1406 G06
Integral Nonlinearity Input Common Mode Rejection Supply Current vs vs Output Code vs Input Frequency Sampling Frequency
1.0 70 35 60 30 0.5 50 25 40 20 0 30 15 INL EOC ERROR (LSB) 20 10 –0.5 SUPPLY CURRENT (mA) COMMON MODE REJECTION (dB) 10 5 –1.0 0 0 0 32 64 96 128 160 192 224 256 100k 1M 10M 100M 100k 1M 10M 20M OUTPUT CODE INPUT FREQUENCY (Hz) SAMPLING FREQUENCY (Hz) 1406 G08 1406 G09 1406 G07
U U U PIN FUNCTIONS OGND (Pin 1):
Digital Data Output Ground. Tie to analog
VREF (Pin 5):
External 2.5V Reference Input. Bypass to ground plane. May be tied to logic ground if desired. analog ground plane with 10µF tantalum in parallel with 0.1µF or 10µF ceramic.
OVDD (Pin 2):
Digital Data Output Supply. Normally tied to 5V, can be used to interface with 3V digital logic. Bypass
AGND (Pin 6):
Analog Ground. Tie to analog ground plane. to OGND with 10µF tantalum in parallel with 0.1µF or 10µF
A + IN (Pin 7):
± 1V Input. The maximum output code ceramic. occurs when [(A + – IN ) – (AIN )] = 1V. The minimum output
SHDN (Pin 3):
Power Shutdown Input. Logic low selects code occurs when [(A + – IN ) – (AIN )] = – 1V. shutdown.
A – IN (Pin 8):
± 1V Input. The maximum output code
V
occurs when [(A +) – (A –)] = 1V. The minimum output
BIAS (Pin 4):
Internal Bias Voltage. Internally set to 2.2V. IN IN Bypass to analog ground plane with 10µF tantalum in par- code occurs when [(A + – IN ) – (AIN )] = – 1V. For single- allel with 0.1µF or 10µF ceramic. ended operation, tie A – IN to a DC voltage (e.g., VREF). 5
W U TYPICAL PERFORMANCE CHARACTERISTICS Spurious-Free Dynamic Range Differential Nonlinearity vs Input Frequency Intermodulation Distortion Plot vs Output Code
70 0 1.0 f –10 SAMPLE = 20MHz 60 fIN1 = 3.500977MHz –20 fIN2 = 3.598633MHz 0.5 50 –30 40 –40 –50 0 30 –60 AMPLITUDE (dB) 20 –70 DNL EOC ERROR (LSB) –0.5 –80 10 SPURIOUS-FREE DYNAMIC RANGE (dB) –90 0 –100 –1.0 100k 1M 10M 100M 0 1 2 3 4 5 6 7 8 9 10 0 32 64 96 128 160 192 224 256 INPUT FREQUENCY (Hz) FREQUENCY (MHz) OUTPUT CODE 1406 G04 1406 G05 1406 G06
Integral Nonlinearity Input Common Mode Rejection Supply Current vs vs Output Code vs Input Frequency Sampling Frequency
1.0 70 35 60 30 0.5 50 25 40 20 0 30 15 INL EOC ERROR (LSB) 20 10 –0.5 SUPPLY CURRENT (mA) COMMON MODE REJECTION (dB) 10 5 –1.0 0 0 0 32 64 96 128 160 192 224 256 100k 1M 10M 100M 100k 1M 10M 20M OUTPUT CODE INPUT FREQUENCY (Hz) SAMPLING FREQUENCY (Hz) 1406 G08 1406 G09 1406 G07
U U U PIN FUNCTIONS OGND (Pin 1):
Digital Data Output Ground. Tie to analog
VREF (Pin 5):
External 2.5V Reference Input. Bypass to ground plane. May be tied to logic ground if desired. analog ground plane with 10µF tantalum in parallel with 0.1µF or 10µF ceramic.
OVDD (Pin 2):
Digital Data Output Supply. Normally tied to 5V, can be used to interface with 3V digital logic. Bypass
AGND (Pin 6):
Analog Ground. Tie to analog ground plane. to OGND with 10µF tantalum in parallel with 0.1µF or 10µF
A + IN (Pin 7):
± 1V Input. The maximum output code ceramic. occurs when [(A + – IN ) – (AIN )] = 1V. The minimum output
SHDN (Pin 3):
Power Shutdown Input. Logic low selects code occurs when [(A + – IN ) – (AIN )] = – 1V. shutdown.
A – IN (Pin 8):
± 1V Input. The maximum output code
V
occurs when [(A +) – (A –)] = 1V. The minimum output
BIAS (Pin 4):
Internal Bias Voltage. Internally set to 2.2V. IN IN Bypass to analog ground plane with 10µF tantalum in par- code occurs when [(A + – IN ) – (AIN )] = – 1V. For single- allel with 0.1µF or 10µF ceramic. ended operation, tie A – IN to a DC voltage (e.g., VREF). 5