Datasheet LTC1405 (Analog Devices) - 9

LTC1405
U U W U APPLICATIO S I FOR ATIO Conversion Details Analog Input Ranges
The LTC1405 is a high performance 12-bit A/D converter The LTC1405 has a flexible analog input with a wide that operates up to 5Msps. It is a complete solution with selection of input ranges. The input range is always an on-chip sample-and-hold, a 12-bit pipelined CMOS differential and is set by the voltages at the VREF and the ADC, a low drift programmable reference and an input GAIN pins (Figure 1). The input range of the A/D core is programmable gain amplifier. The digital output is paral- fixed at ±VREF/2. The reference voltage, VREF, is either set lel, with a 12-bit two’s complement format and an out-of- by the on-chip voltage reference or directly driven by an range (overflow) bit. external voltage. The GAIN pin is a digital input that controls the gain of a preamplifier in the sample-and-hold The rising edge of the CLK begins the conversion. The circuit. The gain of this PGA can be set to 1x or 2x. Table 1 differential analog inputs are simultaneously sampled and gives the input range in terms of V passed on to the pipelined A/D. After two more conversion REF and GAIN. starts (plus a 150ns conversion time) the digital outputs
Table 1
are updated with the conversion result and will be ready for
INPUT RANGE + –
capture on the third rising clock edge. Thus even though
GAIN PIN PGA GAIN (VIN = AIN – AIN )
a new conversion is begun every time CLK goes high, each 5V (Logic H) 1x – VREF/2 < VIN < VREF/2 result takes three clock cycles to reach the output. OV (Logic L) 2x – VREF/4 < VIN < VREF/4 The analog signals that are passed from stage to stage in GAIN the pipelined A/D are stored on capacitors. The signals on 1x/2x these capacitors will be lost if the delay between conver- sions is too long. For accurate conversion results, the part +AIN + should be clocked faster than 20kHz. V ADC IN PGA S/H ±VREF/2 –A CORE IN – In some pipelined A/D converters if there is no clock present, dynamic logic on the chip will droop and the VREF 1405 F01 power consumption sharply increases. The LTC1405 doesn’t have this problem. If the part is not clocked for
Figure 1. Analog Input Circuit
1ms, an internal timer will refresh the dynamic logic. Thus
Internal Reference
the clock can be turned off for long periods of time to save power. Figure 2 shows a simplified schematic of the LTC1405 reference circuitry. An on-chip temperature compensated
Power Supplies
bandgap reference (VCM) is factory trimmed to 2.500V. The LTC1405 will operate from either a single 5V or dual The voltage at the VREF pin sets the input span of the ADC ±5V supply, making it easy to interface the analog input to to ±VREF/2. An internal voltage divider converts VCM to single or dual supply systems. The digital output drivers 2.048V, which is connected to a reference amplifier. The have their own power supply pin (OV reference programming pin, SENSE, controls how the DD) which can be set from 3V to 5V, allowing direct connection to either 3V or reference amplifier drives the VREF pin. If SENSE is tied to 5V digital systems. For single supply operation, V ground, the reference amplifier feedback is connected to SS should be connected to analog ground. For dual supply operation, the R1/R2 voltage divider, thus making VREF = 4.096V. If V SENSE is tied to VREF, the reference amplifier feedback is SS should be connected to – 5V. Both VDD pins should be connected to a clean 5V analog supply. (Don’t connect V connected to SENSE thus making VREF = 2.048V. If SENSE DD to a noisy system digital supply.) is tied to VDD, the reference amplifier is disconnected from VREF and VREF can be driven by an external voltage. With two additional resistors, VREF can be set to any voltage between 2.048V and 4.5V. 1405fa 9