Datasheet LTC1403-1, LTC1403A-1 (Analog Devices) - 9
| Hersteller | Analog Devices |
| Beschreibung | Serial 14-Bit, 2.8Msps Sampling ADCs with Shutdown |
| Seiten / Seite | 24 / 9 — PIN FUNCTIONS. A +. IN (Pin 1):. A –. IN (Pin 2):. SDO (Pin 8):. REF (Pin … |
| Dateiformat / Größe | PDF / 576 Kb |
| Dokumentensprache | Englisch |
PIN FUNCTIONS. A +. IN (Pin 1):. A –. IN (Pin 2):. SDO (Pin 8):. REF (Pin 3):. SCK (Pin 9):. GND (Pins 4, 5, 6, Exposed Pad Pin 11):
Modelllinie für dieses Datenblatt
Textversion des Dokuments
LTC1403-1/LTC1403A-1
PIN FUNCTIONS A +
+
IN (Pin 1):
Noninverting Analog Input. AIN operates solid analog ground plane with a 10µF ceramic capacitor fully differentially with respect to A – IN with a –1.25V to (or 10µF tantalum in parallel with 0.1µF ceramic). Keep in 1.25V differential swing with respect to A – IN and a 0V to mind that internal analog currents and digital output signal VDD common mode swing. currents flow through this pin. Care should be taken to
A –
– place the 0.1µF bypass capacitor as close to Pins 6 and
IN (Pin 2):
Inverting Analog Input. AIN operates fully differentially with respect to A + 7 as possible. IN with a 1.25V to –1.25V differential swing with respect to A + IN and a 0V to VDD
SDO (Pin 8):
Three-State Serial Data Output. Each of common mode swing. output data words represents the difference between + –
V
AIN and AIN analog inputs at the start of the previous
REF (Pin 3):
2.5V Internal Reference. Bypass to GND and to a solid analog ground plane with a 10µF ceramic conversion. The output format is 2’s complement. capacitor (or 10µF tantalum in parallel with 0.1µF ceramic).
SCK (Pin 9):
External Clock Input. Advances the conver- Can be overdriven by an external reference between 2.55V sion process and sequences the output data on the rising and VDD. edge. Responds to TTL (≤3V) and 3V CMOS levels. One
GND (Pins 4, 5, 6, Exposed Pad Pin 11):
Ground. These or more pulses wake from sleep. ground pins and the exposed pad must be tied directly to
CONV (Pin 10):
Convert Start. Holds the analog input signal the solid ground plane under the part. Keep in mind that and starts the conversion on the rising edge. Responds analog signal currents and digital output signal currents to TTL (≤3V) and 3V CMOS levels. Two pulses with SCK flow through these pins. in fixed high or fixed low state start Nap mode. Four or
V
more pulses with SCK in fixed high or fixed low state start
DD (Pin 7):
3V Positive Supply. This single power pin supplies 3V to the entire chip. Bypass to GND and to a Sleep mode. 14031fd For more information www.linear.com/LTC1403-1 9 Document Outline Features Applications Description Block Diagram Absolute Maximum Ratings Pin Configuration Order Information Converter Characteristics Analog Input Dynamic Accuracy Internal Reference Characteristics Digital Inputs and Digital Outputs Power Requirements Timing Characteristics Typical Performance Characteristics Pin Functions Block Diagram Timing Diagram Applications Information Revision History Related Parts
PIN FUNCTIONS A +
+
IN (Pin 1):
Noninverting Analog Input. AIN operates solid analog ground plane with a 10µF ceramic capacitor fully differentially with respect to A – IN with a –1.25V to (or 10µF tantalum in parallel with 0.1µF ceramic). Keep in 1.25V differential swing with respect to A – IN and a 0V to mind that internal analog currents and digital output signal VDD common mode swing. currents flow through this pin. Care should be taken to
A –
– place the 0.1µF bypass capacitor as close to Pins 6 and
IN (Pin 2):
Inverting Analog Input. AIN operates fully differentially with respect to A + 7 as possible. IN with a 1.25V to –1.25V differential swing with respect to A + IN and a 0V to VDD
SDO (Pin 8):
Three-State Serial Data Output. Each of common mode swing. output data words represents the difference between + –
V
AIN and AIN analog inputs at the start of the previous
REF (Pin 3):
2.5V Internal Reference. Bypass to GND and to a solid analog ground plane with a 10µF ceramic conversion. The output format is 2’s complement. capacitor (or 10µF tantalum in parallel with 0.1µF ceramic).
SCK (Pin 9):
External Clock Input. Advances the conver- Can be overdriven by an external reference between 2.55V sion process and sequences the output data on the rising and VDD. edge. Responds to TTL (≤3V) and 3V CMOS levels. One
GND (Pins 4, 5, 6, Exposed Pad Pin 11):
Ground. These or more pulses wake from sleep. ground pins and the exposed pad must be tied directly to
CONV (Pin 10):
Convert Start. Holds the analog input signal the solid ground plane under the part. Keep in mind that and starts the conversion on the rising edge. Responds analog signal currents and digital output signal currents to TTL (≤3V) and 3V CMOS levels. Two pulses with SCK flow through these pins. in fixed high or fixed low state start Nap mode. Four or
V
more pulses with SCK in fixed high or fixed low state start
DD (Pin 7):
3V Positive Supply. This single power pin supplies 3V to the entire chip. Bypass to GND and to a Sleep mode. 14031fd For more information www.linear.com/LTC1403-1 9 Document Outline Features Applications Description Block Diagram Absolute Maximum Ratings Pin Configuration Order Information Converter Characteristics Analog Input Dynamic Accuracy Internal Reference Characteristics Digital Inputs and Digital Outputs Power Requirements Timing Characteristics Typical Performance Characteristics Pin Functions Block Diagram Timing Diagram Applications Information Revision History Related Parts