Datasheet LTC1403-1, LTC1403A-1 (Analog Devices) - 4

LTC1403-1/LTC1403A-1
DIGITAL INPUTS AND DIGITAL OUTPUTS The
l
denotes the specifications which apply over the full operating temperature range, otherwise specifications are at TA = 25°C. VDD = 3V SYMBOL PARAMETER CONDITIONS MIN TYP MAX UNITS
VIH High Level Input Voltage VDD = 3.3V l 2.4 V VIL Low Level Input Voltage VDD = 2.7V l 0.6 V IIN Digital Input Current VIN = 0V to VDD l ±10 µA CIN Digital Input Capacitance (Note 20) 5 pF VOH High Level Output Voltage VDD = 3V, IOUT = –200µA l 2.5 2.9 V VOL Low Level Output Voltage VDD = 2.7V, IOUT = 160µA 0.05 V VDD = 2.7V, IOUT = 1.6mA l 0.10 0.4 V IOZ Hi-Z Output Leakage DOUT VOUT = 0V to VDD l ±10 µA COZ Hi-Z Output Capacitance DOUT 1 pF ISOURCE Output Short-Circuit Source Current VOUT = 0V, VDD = 3V 20 mA ISINK Output Short-Circuit Sink Current VOUT = VDD = 3V 15 mA
POWER REQUIREMENTS The
l
denotes the specifications which apply over the full operating temperature range, otherwise specifications are at TA = 25°C. (Note 17) SYMBOL PARAMETER CONDITIONS MIN TYP MAX UNITS
VDD Supply Voltage 2.7 3.6 V IDD Positive Supply Voltage Active Mode l 4.7 7 mA Nap Mode l 1.1 1.5 mA Sleep Mode (LTC1403-1) 2 15 µA Sleep Mode (LTC1403A-1) 2 10 µA PD Power Dissipation Active Mode with SCK in Fixed State (Hi or Lo) 12 mW
TIMING CHARACTERISTICS The
l
denotes the specifications which apply over the full operating temperature range, otherwise specifications are at TA = 25°C. VDD = 3V SYMBOL PARAMETER CONDITIONS MIN TYP MAX UNITS
fSAMPLE(MAX) Maximum Sampling Frequency per Channel l 2.8 MHz (Conversion Rate) tTHROUGHPUT Minimum Sampling Period (Conversion + Acquisition Period) l 357 ns tSCK Clock Period (Note 16) l 19.8 10000 ns tCONV Conversion Time (Note 6) 17 18 SCLK cycles t1 Minimum Positive or Negative SCLK Pulse Width (Note 6) 2 ns t2 CONV to SCK Setup Time (Notes 6, 10) 3 ns t3 Nearest SCK Edge Before CONV (Note 6) 0 ns t4 Minimum Positive or Negative CONV Pulse Width (Note 6) 4 ns t5 SCK to Sample Mode (Note 6) 4 ns t6 CONV to Hold Mode (Notes 6, 11) 1.2 ns t7 16th SCK↑ to CONV↑ Interval (Affects Acquisition Period) (Notes 6, 7, 13) 45 ns t8 Minimum Delay from SCK to Valid Data (Notes 6, 12) 8 ns t9 SCK to Hi-Z at SDO (Notes 6, 12) 6 ns t10 Previous SDO Bit Remains Valid After SCK (Notes 6, 12) 2 ns t12 VREF Settling Time After Sleep-to-Wake Transition (Notes 6, 14) 2 ms 14031fd 4 For more information www.linear.com/LTC1403-1 Document Outline Features Applications Description Block Diagram Absolute Maximum Ratings Pin Configuration Order Information Converter Characteristics Analog Input Dynamic Accuracy Internal Reference Characteristics Digital Inputs and Digital Outputs Power Requirements Timing Characteristics Typical Performance Characteristics Pin Functions Block Diagram Timing Diagram Applications Information Revision History Related Parts