Datasheet LTC1402 (Analog Devices) - 4

LTC1402
W U POWER REQUIRE E TS The
●
denotes the specifications which apply over the full operating temperature range, otherwise specifications are at TA = 25
°
C. (Note 5) SYMBOL PARAMETER CONDITIONS MIN TYP MAX UNITS
VDD Positive Supply Voltage 4.75 5.25 V VSS Negative Supply Voltage – 5.25 0 V IDD Positive Supply Current Active Mode ● 18 30 mA Nap Mode ● 3 5 mA Sleep Mode 2 10 µA ISS Negative Supply Current Active, Sleep or Nap Modes with SCK Off ● 2 µA PD Power Dissipation Active Mode with SCK in Fixed State (Hi or Lo) 90 150 mW
W U TI I G CHARACTERISTICS The
●
denotes the specifications which apply over the full operating temperature range, otherwise specifications are at TA = 25
°
C. (Note 5) SYMBOL PARAMETER CONDITIONS MIN TYP MAX UNITS
fSAMPLE(MAX) Maximum Sampling Frequency (Conversion Rate) ● 2.2 MHz tTHROUGHPUT Minimum Sampling Period (Conversion + Acquisiton Period) ● 455 ns tSCK Minimum Clock Period ● 28 10000 ns tCONV Conversion Time (Note 9) 14 SCK cycles t0 14th SCLK↑ to CONV↑ Interval (Notes 9, 10, 16) ● 57 ns t1 Minimum Positive or Negative SCK Pulse Width (Note 9) ● 3.8 6 ns t2 CONV to SCK Setup Time (Notes 9, 13) ● 7.3 12 ns t3 SCK After CONV (Note 9) ● 0 ns t4 Minimum Positive or Negative CONV Pulse Width (Note 9) ● 3.5 5 ns t5 SCK to Sample Mode (Note 9) ● 9 14 ns t6 CONV to Hold Mode (Notes 9, 14) ● 3.4 5 ns t7 Minimum Delay Between Conversions (Note 9) ● 48 ns t8 Minimum Delay from SCK to Valid Bits 0 Through 11 (Notes 9, 15) ● 9 12 ns t8a Minimum Delay from SCK to Valid REFREADY (Notes 9, 15) ● 15 20 ns t9 SCK to Hi-Z at DOUT (Notes 9, 15) ● 11.4 16 ns t10 Previous DOUT Bit Remains Valid After SCK (Notes 9, 15) ● 4 7 ns t11 REFREADY Bit Delay After Sleep-to-Wake Transition (Notes 9, 17) ● 10 ms t12 VREF Settling Time After Sleep-to-Wake Transition (Notes 9, 17) ● 2 ms
Note 1:
Absolute Maximum Ratings are those values beyond which the life
Note 6:
Linearity, offset and full-scale specifications apply for a single- of a device may be impaired. ended A + – IN input with AIN grounded and using the internal reference in
Note 2:
All voltage values are with respect to ground with DGND, AGND1 bipolar mode with ±5V supplies. and AGND2 wired together.
Note 7:
Integral linearity is defined as the deviation of a code from the
Note 3:
When these pins are taken below V straight line passing through the actual endpoints of a transfer curve. The SS or above VDD, they will be clamped by internal diodes. This product can handle input currents greater deviation is measured from the center of quantization band. than 100mA below VSS or greater than VDD without latchup.
Note 8:
Bipolar offset is the offset measured from – 0.5LSB when the input
Note 4:
When these pins are taken below V flickers between 1000 0000 0000 and 0111 1111 1111. SS, they will be clamped by internal diodes. This product can handle input currents greater than
Note 9:
Guaranteed by design, not subject to test. 100mA below VSS or greater than VDD. These pins are not clamped to VDD.
Note 10:
Recommended operating conditions.
Note 5:
VDD = 5V, fSAMPLE = 2.2MHz, VSS = 0V for unipolar mode
Note 11:
The analog input range is defined as the voltage difference specifications and VSS = – 5V for bipolar specifications. between A + – IN and AIN . The bipolar ±2.048V input range could be used with a single 5V supply if the absolute voltages of the inputs remain within the single 5V supply voltage. 4