Datasheet LTC1292, LTC1297 (Analog Devices) - 10
| Hersteller | Analog Devices |
| Beschreibung | Single Chip 12-Bit Data Acquisition Systems |
| Seiten / Seite | 24 / 10 — APPLICATI. S I FOR ATIO. Figure 2. Hardware and Software Interface to … |
| Dateiformat / Größe | PDF / 325 Kb |
| Dokumentensprache | Englisch |
APPLICATI. S I FOR ATIO. Figure 2. Hardware and Software Interface to Motorola MC68HC11 Microcontroller
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LTC1292/LTC1297
O U U W U APPLICATI S I FOR ATIO
DOUT FROM LTC1292 STORED ON MC68HC11 RAM LTC1292 MC68HC11 MSB CS DO LOCATION #61 O O O O B11 B10 B9 B8 BYTE 1 CLK SCK ANALOG INPUTS DOUT MISO LOCATION #62 B7 B6 B5 B4 B3 B2 B1 B0 BYTE 2 LTC1292/7 F02
Figure 2. Hardware and Software Interface to Motorola MC68HC11 Microcontroller MC68HC11 CODE for LTC1292 Interface LABEL MNEMONIC OPERAND COMMENTS LABEL MNEMONIC OPERAND COMMENTS
LDAA #$50 CONFIGURATION DATA FOR SPCR STAB $08, X D0 GOES LOW (CS GOES LOW) STAA $1028 LOAD DATA INTO SPCR ($1028) NOP 6 NOPS FOR TIMING LDAA #$1B CONFIG. DATA FOR PORT D DDR STAA $1009 LOAD DATA INTO PORT D DDR LDAA $1029 CHECK SPI STATUS REG LDAA #$00 LOAD DUMMY DIN WORD INTO LDAA $102A LOAD LTC1292 MSBs INTO ACC A ACC A STAA $61 STORE MSBs IN $61 STAA $50 LOAD DUMMY DIN DATA INTO $50 STAA $102A LOAD DUMMY DIN INTO SPI, LOOP LDX #$1000 LOAD INDEX REGISTER X WITH START SCK $1000 NOPS 6 NOPS FOR TIMING LDAB #$00 LOAD ACC B WITH $00 LDAA $50 LOAD DUMMY DIN INTO ACC A BSET $08,X,$01 D0 GOES HIGH (CS GOES HIGH) FROM $50 LDAA $1029 CHECK SPI STATUS REGISTER STAA $102A LOAD DUMMY DIN INTO SPI, LDAA $102A LOAD LTC1292 LSBs IN ACC START SCK STAA $62 STORE LSBs IN $62 NOP DELAY CS FALL TIME TO RIGHT JUSTIFY DATA JMP LOOP START NEXT CONVERSION the MPU. The data is right-justified in the two memory For the LTC1297 (Figure 3) a delay must be introduced to locations (Figure 2). This was made possible by delaying accommodate the setup time, tsuCS, before the dummy the falling edge of CS till after the second CLK. ANDing the DIN word is sent to the data register. The first 8-bit transfer first byte with 0FHEX clears the four most significant bits. clocks B11 through B6 of the A/D conversion result into This operation was not included in the code. It can be the processor. The second 8-bit transfer clocks the re- inserted in the data gathering loop or outside the loop maining bits B5 through B0 into the MPU. Note B1 and B2 when the data is processed. from the LSB-first data word have also been clocked in. CS CLK DOUT B11 B10 B9 B8 B7 B6 B5 B4 B3 B2 B1 B0 B1 B2 B3 BYTE 1 BYTE 2 MPU ? 0 B11 B10 B9 B8 B7 B6 B5 B4 B3 B2 B1 B0 B1 RECEIVED WORD B2 1ST TRANSFER 2ND TRANSFER LTC1292/7 F03
Figure 3. Data Exchange Between LTC1297 and MC68HC11
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O U U W U APPLICATI S I FOR ATIO
DOUT FROM LTC1292 STORED ON MC68HC11 RAM LTC1292 MC68HC11 MSB CS DO LOCATION #61 O O O O B11 B10 B9 B8 BYTE 1 CLK SCK ANALOG INPUTS DOUT MISO LOCATION #62 B7 B6 B5 B4 B3 B2 B1 B0 BYTE 2 LTC1292/7 F02
Figure 2. Hardware and Software Interface to Motorola MC68HC11 Microcontroller MC68HC11 CODE for LTC1292 Interface LABEL MNEMONIC OPERAND COMMENTS LABEL MNEMONIC OPERAND COMMENTS
LDAA #$50 CONFIGURATION DATA FOR SPCR STAB $08, X D0 GOES LOW (CS GOES LOW) STAA $1028 LOAD DATA INTO SPCR ($1028) NOP 6 NOPS FOR TIMING LDAA #$1B CONFIG. DATA FOR PORT D DDR STAA $1009 LOAD DATA INTO PORT D DDR LDAA $1029 CHECK SPI STATUS REG LDAA #$00 LOAD DUMMY DIN WORD INTO LDAA $102A LOAD LTC1292 MSBs INTO ACC A ACC A STAA $61 STORE MSBs IN $61 STAA $50 LOAD DUMMY DIN DATA INTO $50 STAA $102A LOAD DUMMY DIN INTO SPI, LOOP LDX #$1000 LOAD INDEX REGISTER X WITH START SCK $1000 NOPS 6 NOPS FOR TIMING LDAB #$00 LOAD ACC B WITH $00 LDAA $50 LOAD DUMMY DIN INTO ACC A BSET $08,X,$01 D0 GOES HIGH (CS GOES HIGH) FROM $50 LDAA $1029 CHECK SPI STATUS REGISTER STAA $102A LOAD DUMMY DIN INTO SPI, LDAA $102A LOAD LTC1292 LSBs IN ACC START SCK STAA $62 STORE LSBs IN $62 NOP DELAY CS FALL TIME TO RIGHT JUSTIFY DATA JMP LOOP START NEXT CONVERSION the MPU. The data is right-justified in the two memory For the LTC1297 (Figure 3) a delay must be introduced to locations (Figure 2). This was made possible by delaying accommodate the setup time, tsuCS, before the dummy the falling edge of CS till after the second CLK. ANDing the DIN word is sent to the data register. The first 8-bit transfer first byte with 0FHEX clears the four most significant bits. clocks B11 through B6 of the A/D conversion result into This operation was not included in the code. It can be the processor. The second 8-bit transfer clocks the re- inserted in the data gathering loop or outside the loop maining bits B5 through B0 into the MPU. Note B1 and B2 when the data is processed. from the LSB-first data word have also been clocked in. CS CLK DOUT B11 B10 B9 B8 B7 B6 B5 B4 B3 B2 B1 B0 B1 B2 B3 BYTE 1 BYTE 2 MPU ? 0 B11 B10 B9 B8 B7 B6 B5 B4 B3 B2 B1 B0 B1 RECEIVED WORD B2 1ST TRANSFER 2ND TRANSFER LTC1292/7 F03
Figure 3. Data Exchange Between LTC1297 and MC68HC11
12927fb 10