Datasheet LTC1291 (Analog Devices) - 6

LTC1291
W BLOCK I D AGRA
7 8 CLK VCC (VREF) INPUT OUTPUT 6 5 SHIFT D SHIFT DOUT IN REGISTER REGISTER 2 CH0 SAMPLE ANALOG 3 AND CH1 INPUT MUX HOLD COMP 12-BIT SAR 12-BIT CAPACITIVE DAC CONTROL 1 4 AND CS TIMING GND 1291 BD
TEST CIRCUITS Load Circuit for tdDO, tr and tf Load Circuit for tdis and ten
1.4V TEST POINT 3k 5V t 3k dis WAVEFORM 2, ten DOUT TEST POINT DOUT tdis WAVEFORM 1 100pF 100pF 1291 TC02 1291 TC05
On and Off Channel Leakage Current Voltage Waveforms for tdis
CS 2.0V 5V ION DOUT A ON CHANNEL 90% WAVEFORM 1 (SEE NOTE 1) IOFF tdis A OFF CHANNEL DOUT WAVEFORM 2 10% (SEE NOTE 2) NOTE 1: WAVEFORM 1 IS FOR AN OUTPUT WITH INTERNAL CONDITIONS SUCH THAT THE OUTPUT IS HIGH UNLESS DISABLED BY THE OUTPUT CONTROL. NOTE 2: WAVEFORM 2 IS FOR AN OUTPUT WITH INTERNAL CONDITIONS SUCH POLARITY 1291 TC06 THAT THE OUTPUT IS LOW UNLESS DISABLED BY THE OUTPUT CONTROL. 1291 TC01 1291fa 6