Datasheet LTC1287 (Analog Devices) - 7
| Hersteller | Analog Devices |
| Beschreibung | 3V Single Chip 12-Bit Data Acquisition System |
| Seiten / Seite | 16 / 7 — TEST CIRCUITS. Voltage Waveforms for ten. APPLICATI. S I FOR ATIO. … |
| Dateiformat / Größe | PDF / 328 Kb |
| Dokumentensprache | Englisch |
TEST CIRCUITS. Voltage Waveforms for ten. APPLICATI. S I FOR ATIO. DIGITAL CONSIDERATIONS. Serial Interface. Logic Levels
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LTC1287
TEST CIRCUITS Voltage Waveforms for ten
CS CLK B11 DOUT 0.6V ten LTC1287 TC07
O U U W U APPLICATI S I FOR ATIO
The LTC1287 is a data acquisition component which does not require a configuration input word and has no DIN contains the following functional blocks: pin. It is permanently configured to have a single differen- 1. 12-bit successive approximation capacitive A/D tial input and to operate in unipolar mode. A falling CS converter initiates data transfer. The first CLK pulse enables DOUT. 2. Analog multiplexer (MUX) After one null bit, the A/D conversion result is output on the D 3. Sample-and-hold (S/H) OUT line with a MSB-first sequence followed by a LSB- first sequence. With the half duplex serial interface the 4. Synchronous, half-duplex serial interface DOUT data is from the current conversion. This provides 5. Control and timing logic easy interface to MSB- or LSB-first serial ports. Bringing CS high resets the LTC1287 for the next data exchange.
DIGITAL CONSIDERATIONS Serial Interface Logic Levels
The LTC1287 communicates with microprocessors and The logic level standards for this supply range have not other external circuitry via a synchronous, half-duplex, been well defined. What standards that do exist are not three-wire serial interface (see Operating Sequence). The universally accepted. The trip point on the logic inputs of clock (CLK) synchronizes the data transfer with each bit the LTC1287 is 0.28 × VCC. This makes the logic inputs being transmitted on the falling CLK edge. The LTC1287 compatible with HC-type levels and processors that are tCYC CS CLK Hi-Z D B11 B10 B9 B8 B7 B6 B5 B4 B3 B2 B1 B0 B1 B2 B3 B4 B5 B6 B7 B8 B9 B10 B11 OUT tSMPL tCONV tSMPL LTC1287 F01
Figure 1. LTC1287 Operating Sequence
1287fa 7
TEST CIRCUITS Voltage Waveforms for ten
CS CLK B11 DOUT 0.6V ten LTC1287 TC07
O U U W U APPLICATI S I FOR ATIO
The LTC1287 is a data acquisition component which does not require a configuration input word and has no DIN contains the following functional blocks: pin. It is permanently configured to have a single differen- 1. 12-bit successive approximation capacitive A/D tial input and to operate in unipolar mode. A falling CS converter initiates data transfer. The first CLK pulse enables DOUT. 2. Analog multiplexer (MUX) After one null bit, the A/D conversion result is output on the D 3. Sample-and-hold (S/H) OUT line with a MSB-first sequence followed by a LSB- first sequence. With the half duplex serial interface the 4. Synchronous, half-duplex serial interface DOUT data is from the current conversion. This provides 5. Control and timing logic easy interface to MSB- or LSB-first serial ports. Bringing CS high resets the LTC1287 for the next data exchange.
DIGITAL CONSIDERATIONS Serial Interface Logic Levels
The LTC1287 communicates with microprocessors and The logic level standards for this supply range have not other external circuitry via a synchronous, half-duplex, been well defined. What standards that do exist are not three-wire serial interface (see Operating Sequence). The universally accepted. The trip point on the logic inputs of clock (CLK) synchronizes the data transfer with each bit the LTC1287 is 0.28 × VCC. This makes the logic inputs being transmitted on the falling CLK edge. The LTC1287 compatible with HC-type levels and processors that are tCYC CS CLK Hi-Z D B11 B10 B9 B8 B7 B6 B5 B4 B3 B2 B1 B0 B1 B2 B3 B4 B5 B6 B7 B8 B9 B10 B11 OUT tSMPL tCONV tSMPL LTC1287 F01
Figure 1. LTC1287 Operating Sequence
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