Datasheet LTC1286, LTC1298 (Analog Devices) - 10
| Hersteller | Analog Devices |
| Beschreibung | Micropower Sampling 12-Bit A/D Converters In S0-8 Packages |
| Seiten / Seite | 24 / 10 — APPLICATION INFORMATION. SERIAL INTERFACE. Data Transfer. Figure 1. … |
| Dateiformat / Größe | PDF / 299 Kb |
| Dokumentensprache | Englisch |
APPLICATION INFORMATION. SERIAL INTERFACE. Data Transfer. Figure 1. LTC1286 Operating Sequence
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LTC1286/LTC1298
U U W U APPLICATION INFORMATION SERIAL INTERFACE
A/D conversion result is output on the DOUT line. Bringing CS high resets the LTC1286 for the next data exchange. The 2-channel LTC1298 communicates with micropro- cessors and other external circuitry via a synchronous, The LTC1298 first receives input data and then transmits half duplex, 4-wire serial interface. The single channel back the A/D conversion result (half duplex). Because of LTC1286 uses a 3-wire interface (see Operating Sequence the half duplex operation, DIN and DOUT may be tied in Figures 1 and 2). together allowing transmission over just 3 wires: CS, CLK and DATA (DIN/DOUT).
Data Transfer
Data transfer is initiated by a falling chip select (CS) signal. The CLK synchronizes the data transfer with each bit being After CS falls the LTC1298 looks for a start bit. After the transmitted on the falling CLK edge and captured on the start bit is received, the 3-bit input word is shifted into the rising CLK edge in both transmitting and receiving systems. DIN input which configures the LTC1298 and starts the The LTC1286 does not require a configuration input word conversion. After one null bit, the result of the conversion and has no DIN pin. A falling CS initiates data transfer as is output on the DOUT line. At the end of the data exchange shown in the LTC1286 operating sequence. After CS falls CS should be brought high. This resets the LTC1298 in the second CLK pulse enables DOUT. After one null bit the preparation for the next data exchange. tCYC CS t POWER suCS DOWN CLK HI-Z NULL NULL HI-Z DOUT BIT B11 B10 B9 B8 B7 B6 B5 B4 B3 B2 B1 B0* BIT B11 B10 B9 B8 t (MSB) SMPL tCONV tDATA *AFTER COMPLETING THE DATA TRANSFER, IF FURTHER CLOCKS ARE APPLIED WITH CS LOW, THE ADC WILL OUTPUT LSB-FIRST DATA THEN FOLLOWED WITH ZEROS INDEFINITELY. tCYC CS t POWER DOWN suCS CLK NULL HI-Z BIT HI-Z DOUT B11 B10 B9 B8 B7 B6 B5 B4 B3 B2 B1 B0 B1 B2 B3 B4 B5 B6 B7 B8 B9 B10 B11* (MSB) tSMPL tCONV tDATA *AFTER COMPLETING THE DATA TRANSFER, IF FURTHER CLOCKS ARE APPLIED WITH CS LOW, THE ADC WILL OUTPUT ZEROS INDEFINITELY. t DATA: DURING THIS TIME, THE BIAS CIRCUIT AND THE COMPARATOR POWER DOWN AND THE REFERENCE INPUT LTC1286/98 • F01 BECOMES A HIGH IMPEDANCE NODE, LEAVING THE CLK RUNNING TO CLOCK OUT LSB-FIRST DATA OR ZEROES.
Figure 1. LTC1286 Operating Sequence
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U U W U APPLICATION INFORMATION SERIAL INTERFACE
A/D conversion result is output on the DOUT line. Bringing CS high resets the LTC1286 for the next data exchange. The 2-channel LTC1298 communicates with micropro- cessors and other external circuitry via a synchronous, The LTC1298 first receives input data and then transmits half duplex, 4-wire serial interface. The single channel back the A/D conversion result (half duplex). Because of LTC1286 uses a 3-wire interface (see Operating Sequence the half duplex operation, DIN and DOUT may be tied in Figures 1 and 2). together allowing transmission over just 3 wires: CS, CLK and DATA (DIN/DOUT).
Data Transfer
Data transfer is initiated by a falling chip select (CS) signal. The CLK synchronizes the data transfer with each bit being After CS falls the LTC1298 looks for a start bit. After the transmitted on the falling CLK edge and captured on the start bit is received, the 3-bit input word is shifted into the rising CLK edge in both transmitting and receiving systems. DIN input which configures the LTC1298 and starts the The LTC1286 does not require a configuration input word conversion. After one null bit, the result of the conversion and has no DIN pin. A falling CS initiates data transfer as is output on the DOUT line. At the end of the data exchange shown in the LTC1286 operating sequence. After CS falls CS should be brought high. This resets the LTC1298 in the second CLK pulse enables DOUT. After one null bit the preparation for the next data exchange. tCYC CS t POWER suCS DOWN CLK HI-Z NULL NULL HI-Z DOUT BIT B11 B10 B9 B8 B7 B6 B5 B4 B3 B2 B1 B0* BIT B11 B10 B9 B8 t (MSB) SMPL tCONV tDATA *AFTER COMPLETING THE DATA TRANSFER, IF FURTHER CLOCKS ARE APPLIED WITH CS LOW, THE ADC WILL OUTPUT LSB-FIRST DATA THEN FOLLOWED WITH ZEROS INDEFINITELY. tCYC CS t POWER DOWN suCS CLK NULL HI-Z BIT HI-Z DOUT B11 B10 B9 B8 B7 B6 B5 B4 B3 B2 B1 B0 B1 B2 B3 B4 B5 B6 B7 B8 B9 B10 B11* (MSB) tSMPL tCONV tDATA *AFTER COMPLETING THE DATA TRANSFER, IF FURTHER CLOCKS ARE APPLIED WITH CS LOW, THE ADC WILL OUTPUT ZEROS INDEFINITELY. t DATA: DURING THIS TIME, THE BIAS CIRCUIT AND THE COMPARATOR POWER DOWN AND THE REFERENCE INPUT LTC1286/98 • F01 BECOMES A HIGH IMPEDANCE NODE, LEAVING THE CLK RUNNING TO CLOCK OUT LSB-FIRST DATA OR ZEROES.
Figure 1. LTC1286 Operating Sequence
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