Datasheet LTC1274, LTC1277 (Analog Devices) - 9
| Hersteller | Analog Devices |
| Beschreibung | 12-Bit, 10mW, 100ksps ADCs with 1µA Shutdown |
| Seiten / Seite | 20 / 9 — BLOCK DIAGRA S. LTC1274. LTC1277. TEST CIRCUITS. Load Circuits for Access … |
| Dateiformat / Größe | PDF / 241 Kb |
| Dokumentensprache | Englisch |
BLOCK DIAGRA S. LTC1274. LTC1277. TEST CIRCUITS. Load Circuits for Access Timing. Load Circuits for Output Float Delay
Modelllinie für dieses Datenblatt
Textversion des Dokuments
LTC1274/LTC1277
W BLOCK DIAGRA S LTC1274
CSAMPLE A V IN DD ZEROING SWITCHES V V REF SS (0V FOR UNIPOLAR MODE OR 2.42V REF –5V FOR BIPOLAR MODE) REFRDY COMPARATOR 12-BIT CAPACITIVE DAC AGND DGND 12 SUCCESSIVE APPROXIMATION • D11 OUTPUT LATCHES • REGISTER • D0 INTERNAL CONTROL LOGIC CLOCK LTC1274 • BD SLEEP CONVST RD CS BUSY
LTC1277
CSAMPLE A + IN VDD A – IN ZEROING SWITCHES V V REF SS (0V FOR UNIPOLAR MODE OR 2.42V REF –5V FOR BIPOLAR MODE) REFRDY COMPARATOR 12-BIT CAPACITIVE DAC AGND DGND 12 D7 SUCCESSIVE APPROXIMATION • • REGISTER OUTPUT LATCHES • • • D1/9 D0/8 INTERNAL CONTROL LOGIC CLOCK LTC1277 • BD HBEN SLEEP NAP CONVST RD CS BUSY VLOGIC 3V OR 5V
TEST CIRCUITS Load Circuits for Access Timing Load Circuits for Output Float Delay
5V 5V 3k 3k DBN DBN DBN DBN 3k CL CL 3k 10pF 10pF DGND DGND DGND DGND A) HIGH-Z TO VOH (t9) B) HIGH-Z TO VOL (t9) A) VOH TO HIGH-Z B) VOL TO HIGH-Z AND VOL TO VOH (t6) AND VOH TO VOL (t6) 1274/77 • TC02 1274/77 • TC01 9
W BLOCK DIAGRA S LTC1274
CSAMPLE A V IN DD ZEROING SWITCHES V V REF SS (0V FOR UNIPOLAR MODE OR 2.42V REF –5V FOR BIPOLAR MODE) REFRDY COMPARATOR 12-BIT CAPACITIVE DAC AGND DGND 12 SUCCESSIVE APPROXIMATION • D11 OUTPUT LATCHES • REGISTER • D0 INTERNAL CONTROL LOGIC CLOCK LTC1274 • BD SLEEP CONVST RD CS BUSY
LTC1277
CSAMPLE A + IN VDD A – IN ZEROING SWITCHES V V REF SS (0V FOR UNIPOLAR MODE OR 2.42V REF –5V FOR BIPOLAR MODE) REFRDY COMPARATOR 12-BIT CAPACITIVE DAC AGND DGND 12 D7 SUCCESSIVE APPROXIMATION • • REGISTER OUTPUT LATCHES • • • D1/9 D0/8 INTERNAL CONTROL LOGIC CLOCK LTC1277 • BD HBEN SLEEP NAP CONVST RD CS BUSY VLOGIC 3V OR 5V
TEST CIRCUITS Load Circuits for Access Timing Load Circuits for Output Float Delay
5V 5V 3k 3k DBN DBN DBN DBN 3k CL CL 3k 10pF 10pF DGND DGND DGND DGND A) HIGH-Z TO VOH (t9) B) HIGH-Z TO VOL (t9) A) VOH TO HIGH-Z B) VOL TO HIGH-Z AND VOL TO VOH (t6) AND VOH TO VOL (t6) 1274/77 • TC02 1274/77 • TC01 9