Datasheet LTC1099 (Analog Devices) - 8
| Hersteller | Analog Devices |
| Beschreibung | High Speed 8-Bit A/D Converter with Built-In Sample-and-Hold |
| Seiten / Seite | 16 / 8 — FUNCTIONAL DESCRIPTIO. Figure 6. Six Input Switched Capacitor Comparator |
| Dateiformat / Größe | PDF / 204 Kb |
| Dokumentensprache | Englisch |
FUNCTIONAL DESCRIPTIO. Figure 6. Six Input Switched Capacitor Comparator
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LTC1099
U U U FUNCTIONAL DESCRIPTIO
T+ T–1 T–2 T T (+) Z Z VIN C1 (–) MS TAP (–) DAC VIRTUAL GROUND (+) 0.5 LSB C2 (–) 0V C1 = C2 (–) LS TAP HOLD TZ SAMPLE SAMPLE T+ T–1 T–2 STROBE 1099 F06
Figure 6. Six Input Switched Capacitor Comparator
also that variations in the bias voltage with time and This holds the DAC output constant for the next step — the temperature will also be rejected. In this state, C1 charges LS conversion. The LS conversion is started when T–1 is to VIN. When TZ opens, VIN is held on C1. opened and T–2 is closed. Capacitor C1 subtracts the 4-bit The next step is the first comparison — the MS-Flash. T DAC approximation from VIN and inputs the difference Z and T+ are opened and T charge to the virtual ground node. The equation for each –1 is closed. The equation for each comparator is: comparator is: V VIN + 0.5LSB – VDAC – LSTAP = 0V IN + 0.5LSB – MSTAP = 0V There are 16 identical comparators each tied to the tap on The 4-bit DAC approximation is input to all 16 compara- a 16 resistor ladder. The MS tap voltages vary from V tors. The LS tap voltages are converted to charge by REF to 0V in 16 equal steps of V capacitor C2. LS taps vary from VREF/16V to 0V in 16 equal REF/16. steps of VREF/256. The comparators look at the net charge Notice that capacitor C2 adds 0.5LSB to VIN. This offsets on the virtual ground node to perform the LS-Flash con- the converter transfer function by 0.5LSB, equally distrib- version. When this conversion is complete, the four LSBs uting the 1LSB quantization error to ±0.5LSB. along with the four MSBs are transferred to the output The outputs of the 16 comparators are temporarily latched latches. In this way, all eight outputs will change and drive the 4-bit DAC directly without need of decoding. simultaneously. 8
U U U FUNCTIONAL DESCRIPTIO
T+ T–1 T–2 T T (+) Z Z VIN C1 (–) MS TAP (–) DAC VIRTUAL GROUND (+) 0.5 LSB C2 (–) 0V C1 = C2 (–) LS TAP HOLD TZ SAMPLE SAMPLE T+ T–1 T–2 STROBE 1099 F06
Figure 6. Six Input Switched Capacitor Comparator
also that variations in the bias voltage with time and This holds the DAC output constant for the next step — the temperature will also be rejected. In this state, C1 charges LS conversion. The LS conversion is started when T–1 is to VIN. When TZ opens, VIN is held on C1. opened and T–2 is closed. Capacitor C1 subtracts the 4-bit The next step is the first comparison — the MS-Flash. T DAC approximation from VIN and inputs the difference Z and T+ are opened and T charge to the virtual ground node. The equation for each –1 is closed. The equation for each comparator is: comparator is: V VIN + 0.5LSB – VDAC – LSTAP = 0V IN + 0.5LSB – MSTAP = 0V There are 16 identical comparators each tied to the tap on The 4-bit DAC approximation is input to all 16 compara- a 16 resistor ladder. The MS tap voltages vary from V tors. The LS tap voltages are converted to charge by REF to 0V in 16 equal steps of V capacitor C2. LS taps vary from VREF/16V to 0V in 16 equal REF/16. steps of VREF/256. The comparators look at the net charge Notice that capacitor C2 adds 0.5LSB to VIN. This offsets on the virtual ground node to perform the LS-Flash con- the converter transfer function by 0.5LSB, equally distrib- version. When this conversion is complete, the four LSBs uting the 1LSB quantization error to ±0.5LSB. along with the four MSBs are transferred to the output The outputs of the 16 comparators are temporarily latched latches. In this way, all eight outputs will change and drive the 4-bit DAC directly without need of decoding. simultaneously. 8