Datasheet LTC1096, LTC1096L, LTC1098, LTC1098L (Analog Devices) - 7

HerstellerAnalog Devices
BeschreibungMicropower Sampling 8-Bit Serial I/O A/D Converters
Seiten / Seite32 / 7 — DIGITAL AND DC ELECTRICAL CHARACTERISTICS. LTC1096L/LTC1098L The
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DokumentenspracheEnglisch

DIGITAL AND DC ELECTRICAL CHARACTERISTICS. LTC1096L/LTC1098L The

DIGITAL AND DC ELECTRICAL CHARACTERISTICS LTC1096L/LTC1098L The

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LTC1096/LTC1096L LTC1098/LTC1098L
DIGITAL AND DC ELECTRICAL CHARACTERISTICS LTC1096L/LTC1098L The
l
denotes the specifi cations which apply over the full operating temperature range, otherwise specifi cations are at TA = 25°C. VCC = 2.65V, VREF = 2.5V, fCLK = 250kHz, unless otherwise noted. SYMBOL PARAMETER CONDITIONS MIN TYP MAX UNITS
VIH High Level Input Voltage VCC = 3.6V l 1.9 V VIL Low Level Input Voltage VCC = 2.65V l 0.45 V IIH High Level Input Current VIN = VCC l 2.5 μA IIL Low Level Input Current VIN = 0V l –2.5 μA VOH High Level Output Voltage VCC = 2.65V, IO = 10μA l 2.3 2.64 V VCC = 2.65V, IO = 360μA l 2.1 2.50 V VOL Low Level Output Voltage VCC = 2.65V, IO = 400μA l 0.3 V IOZ Hi-Z Output Leakage CS ≥ High l ±3.0 μA ISOURCE Output Source Current VOUT = 0V –10 mA ISINK Output Sink Current VOUT = VCC 15 mA IREF Reference Current CS = VCC l 0.001 2.5 μA tCYC ≥ 200μs, fCLK ≤ 50kHz l 3.500 7.5 μA tCYC = 58μs, fCLK = 250kHz l 35.000 50.0 μA ICC Supply Current CS = VCC l 0.001 3.0 μA LTC1096L, tCYC ≥ 200μs, fCLK ≤ 50kHz l 40 80 μA LTC1096L, tCYC = 58μs, fCLK = 250kHz l 120 180 μA LTC1098L, tCYC ≥ 200μs, fCLK ≤ 50kHz l 44 88 μA LTC1098L, tCYC = 58μs, fCLK = 250kHz l 155 230 μA
AC CHARACTERISTICS LTC1096/LTC1098 The
l
denotes the specifi cations which apply over the full operating temperature range, otherwise specifi cations are at TA = 25°C. VCC = 5V, VREF = 5V, fCLK = 500kHz, unless otherwise noted. SYMBOL PARAMETER CONDITIONS MIN TYP MAX UNITS
tSMPL Analog Input Sample Time See Operating Sequence 1.5 CLK Cycles fSMPL(MAX) Maximum Sampling Frequency l 33 kHz tCONV Conversion Time See Operating Sequence 8 CLK Cycles tdDO Delay Time, CLK↓ to DOUT Data Valid See Test Circuits l 200 450 ns tdis Delay Time, CS↑ to DOUT Hi-Z See Test Circuits l 170 450 ns ten Delay Time, CLK↓ to DOUT Enable See Test Circuits l 60 250 ns thDO Time Output Data Remains Valid After CLK↓ CLOAD = 100pF 180 ns tf DOUT Fall Time See Test Circuits l 70 250 ns tr DOUT Rise Time See Test Circuits l 25 100 ns CIN Input Capacitance Analog Inputs On Channel 25 pF Analog Inputs Off Channel 5 pF Digital Input 5 pF 10968fc 7