Datasheet AD825 (Analog Devices) - 8

AD825 80 30 RL = 1k 75 B) d V 20 S = ±15V 70 RL = 150 OOP GAIN ( L VS = ±5V 10 OPEN- 65 OUTPUT VOLTAGE (V p-p) 60
-014 -011
0 10 1k 10k 10k 100k 1M 10M LOAD RESISTANCE ( ) FREQUENCY (Hz)
00876-E 00876-E Figure 13. Open-Loop Gain vs. Load Resistance Figure 16. Large Signal Frequency Response; G = +2
10 200 0 180 –10 160 –PSRR –20 140 120 0.01% ) –30 B +PSRR 0.01% d ( –40 100 0.1% 0.1% PSR –50 80 –60 SETTLING TIME (ns) 60 –70 40 –80 20 –90
-012
0
-015
10k 100k 1M 10M 10 8 6 4 2 0 –2 –4 –6 –8 –10 FREQUENCY (Hz)
00876-E
OUTPUT SWING (0 to ±V)
00876-E Figure 14. Power Supply Rejection vs. Frequency Figure 17. Output Swing and Error vs. Settling Time
130 –50 120 –55 110 100 –60 VS = ±15V B) SECOND 90 d –65 80 VS = ±5V THIRD CMR (dB) –70 70 DISTORTION ( 60 –75 50 –80 40 30
-013
–85
-016
10 100 1k 10k 100k 1M 10M 100k 1M 10M FREQUENCY (Hz)
00876-E
FREQUENCY (Hz)
00876-E Figure 15. Common-Mode Rejection vs. Frequency Figure 18. Harmonic Distortion vs. Frequency Rev. F | Page 7 of 12 Document Outline Features Applications Connection Diagrams General Description Table of Contents Revision History Specifications Absolute Maximum Ratings Pin Configurations ESD Caution Typical Performance Characteristics Driving Capacitive Loads Theory of Operation Input Consideration Grounding and Bypassing Second-Order Low-Pass Filter Outline Dimensions Ordering Guide