link to page 12 link to page 12 link to page 12 Data SheetAD8057/AD80580100mV–0.1–0.2–0.320mV/DIVA)–0.4(µ I B+IB @ ±5V–0.5+IB @ ±2.5V–I–0.6B @ ±2.5V–IB @ ±5V+I–IB @ ±1.5VB @ ±1.5V–0.7–0.8–100mV 016 –40 –30 –20 –1001020304050607080 85 012 4ns/DIVTEMPERATURE (°C) 01064- 01064- Figure 12. Input Bias Current vs. Temperature Figure 15. Small Signal Step Response G = +1, RL = 1 kΩ, VS = ±5 V, See Figure 41 for Test Circuit 45V3PSRR @ ±1.5V ±5V1V/DIVV) V/(m 2RPSR10–5V 017 –40 –30 –20 –1001020304050607080 85 013 4ns/DIVTEMPERATURE (°C) 01064- 01064- Figure 13. PSRR vs. Temperature Figure 16. Large Signal Step Response G = +1,RL = 1 kΩ, VS = ±5.0 V, See Figure 41 for Test Circuit 0100mV–10–2020mV/DIV–PSRR VS = ±2.5VB) d–300VRR ( S+PSRR VS = ±2.5VP–40–50–60–100mV 019 0.11101001000 014 4ns/DIVFREQUENCY (MHz) 01064- 01064- Figure 14. PSRR vs. Frequency Figure 17. Small Signal Step Response G = –1, RL = 1 kΩ, See Figure 42 for Test Circuit Rev. E | Page 7 of 16 Document Outline Features Applications Connection Diagrams General Description Table of Contents Revision History Specifications Absolute Maximum Ratings Maximum Power Dissipations ESD Caution Typical Performance Characteristics Test Circuits Applications Information Driving Capacitive Loads Video Filter Differential Analog-to-Digital Driver Layout Outline Dimensions Ordering Guide