Datasheet AD8027, AD8028 (Analog Devices) - 3

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Data Sheet AD8027/AD8028 SPECIFICATIONS
VS = ±5 V at TA = 25°C, RL = 1 kΩ to midsupply, G = +1, unless otherwise noted.
Table 1. Parameter Test Conditions/Comments Min Typ Max Unit
DYNAMIC PERFORMANCE −3 dB Bandwidth G = +1, V = 0.2 V p-p 138 190 MHz OUT AD8028W only: T to T 138 MHz MIN MAX G = +1, V = 2 V p-p 20 32 MHz OUT AD8028W only: T to T 20 MHz MIN MAX Bandwidth for 0.1 dB Flatness G = +2, V = 0.2 V p-p 16 MHz OUT Slew Rate G = +1, V = 2 V step 90 V/µs OUT G = −1, V = 2 V step 100 V/µs OUT Settling Time to 0.1% G = +2, V = 2 V step 35 ns OUT NOISE/DISTORTION PERFORMANCE Spurious-Free Dynamic Range f = 1 MHz, V = 2 V p-p, R = 24.9 Ω 120 dBc C OUT F (SFDR) f = 5 MHz, V = 2 V p-p, R = 24.9 Ω 80 dBc C OUT F Input Voltage Noise f = 100 kHz 4.3 nV/√Hz Input Current Noise f = 100 kHz 1.6 pA/√Hz Differential Gain Error NTSC, G = +2, R = 150 Ω 0.1 % L Differential Phase Error NTSC, G = +2, R = 150 Ω 0.2 Degrees L Crosstalk, Output to Output G = +1, R = 100 Ω, V = 2 V p-p, V = ±5 V at 1 MHz −93 dB L OUT S DC PERFORMANCE Input Offset Voltage DISABLE/SELECT = tristate or open, PNP active 200 800 µV AD8028W only: T to T 850 µV MIN MAX DISABLE/SELECT = high, NPN active 240 900 µV AD8028W only: T to T 900 µV MIN MAX Input Offset Voltage Drift T to T 1.50 µV/°C MIN MAX Input Bias Current1 V = 0 V, NPN active 4 6 µA CM T to T 4 µA MIN MAX AD8028W only: T to T 6 µA MIN MAX V = 0 V, PNP active −8 −11 µA CM T to T −8 µA MIN MAX AD8028W only: T to T −11 µA MIN MAX Input Offset Current AD8028W only: T to T ±0.1 ±0.9 µA MIN MAX Open-Loop Gain V = ±2.5 V, AD8028W only: T to T 100 110 dB OUT MIN MAX INPUT CHARACTERISTICS Input Impedance 6 MΩ Input Capacitance 2 pF Input Common-Mode Voltage −5.2 to +5.2 V Range Common-Mode Rejection Ratio V = ±2.5 V 90 110 dB CM AD8028W only: T to T 88 dB MIN MAX DISABLE/SELECT PIN Selection Input Voltage Crossover Low T to T −3.0 V MIN MAX Crossover High2 Tristate < ±20 µA, T to T −3.9 to −3.7 V MIN MAX Disable Input Voltage T to T −4.6 V MIN MAX Disable Switching Speed 50% of input to <10% of final V 980 ns OUT Enable Switching Speed 45 ns Rev. D | Page 3 of 27 Document Outline FEATURES APPLICATIONS GENERAL DESCRIPTION PIN CONNECTION DIAGRAM TABLE OF CONTENTS REVISION HISTORY SPECIFICATIONS ABSOLUTE MAXIMUM RATINGS MAXIMUM POWER DISSIPATION Output Short Circuit ESD CAUTION PIN CONFIGURATIONS AND FUNCTION DESCRIPTIONS TYPICAL PERFORMANCE CHARACTERISTICS TEST CIRCUIT THEORY OF OPERATION INPUT STAGE CROSSOVER SELECTION OUTPUT STAGE DC ERRORS WIDEBAND OPERATION CIRCUIT CONSIDERATIONS Balanced Input Impedances PCB Layout Grounding Power Supply Bypassing APPLICATIONS INFORMATION USING THE /DISABLE SELECT PIN DRIVING A 16-BIT ADC BAND-PASS FILTER DESIGN TOOLS AND TECHNICAL SUPPORT OUTLINE DIMENSIONS ORDERING GUIDE AUTOMOTIVE PRODUCTS