Datasheet AD7771 (Analog Devices) - 5

AD7771 Data Sheet FUNCTIONAL BLOCK DIAGRAM AVDD1x REF_OUT REFx+ REFx– AVDD2x AREGxCAP IOVDD DREGCAP COMMON- XTAL1 VCM MODE ANALOG DIGITAL LDO LDO XTAL2/MCLK VOLTAGE CLOCK MANAGER SYNC_IN 2.5V REF SYNC_OUT AIN0+ START AIN0– SINC3/ GAIN 280mV p-p PGA Σ-Δ ADC SINC5 SRC OFFSET DCLK EXT_REF FILTER INT_REF DRDY DATA OUTPUT DOUT3 AIN1+ SINC3/ GAIN INTERFACE PGA Σ-Δ ADC SINC5 DOUT2 AIN1– SRC OFFSET FILTER DOUT1 REFERENCES DOUT0 AIN2+ SINC3/ GAIN REGISTER MAP PGA Σ-Δ ADC SINC5 AND AIN2– SRC OFFSET LOGIC CONTROL RESET REFERENCES FILTER FORMAT1 AIN3+ SINC3/ GAIN PGA Σ-Δ ADC SINC5 FORMAT0 AIN3– SRC OFFSET FILTER HARDWARE MODE3/ALERT REFERENCES MODE MODE2/GPIO2 CONFIGURATION AIN4+ SINC3/ MODE1/GPIO1 PGA Σ-Δ ADC SINC5 GAIN AIN4– SRC OFFSET MODE0/GPIO0 REFERENCES FILTER AIN5+ SINC3/ PGA Σ-Δ ADC SINC5 GAIN SRC OFFSET ALERT/CS AIN5– REFERENCES FILTER DCLK2/SCLK SPI INTERFACE DCLK1/SDI AIN6+ SINC3/ GAIN DCLK0/SDO SINC5 AIN6– PGA Σ-Δ ADC SRC OFFSET REFERENCES FILTER AIN7+ SINC3/ SINC5 GAIN AIN7– PGA Σ-Δ ADC SRC OFFSET REFERENCES FILTER AUXAIN+ AUXAIN– AD7771 SAR ADC DIAGNOSTIC INPUTS
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AVSSx AVDD4 CONVST_SAR
13802- Figure 1. Rev. 0 | Page 4 of 98 Document Outline FEATURES APPLICATIONS GENERAL DESCRIPTION TABLE OF CONTENTS REVISION HISTORY FUNCTIONAL BLOCK DIAGRAM SPECIFICATIONS DOUTx TIMING CHARACTERISTISTICS SPI TIMING CHARACTERISTISTICS SYNCHRONIZATION PINS AND RESET TIMING CHARACTERISTICS SAR ADC TIMING CHARACTERISTISTICS GPIO SRC UPDATE TIMING CHARACTERISTISTICS ABSOLUTE MAXIMUM RATINGS THERMAL RESISTANCE ESD CAUTION PIN CONFIGURATION AND FUNCTION DESCRIPTIONS TYPICAL PERFORMANCE CHARACTERISTICS TERMINOLOGY THEORY OF OPERATION ANALOG INPUTS TRANSFER FUNCTION CORE SIGNAL CHAIN CAPACITIVE PGA INTERNAL REFERENCE AND REFERENCE BUFFERS INTEGRATED LDOs CLOCKING AND SAMPLING DIGITAL RESET AND SYNCHRONIZATION PINS DIGITAL FILTERING SHUTDOWN MODE CONTROLLING THE AD7771 PIN CONTROL MODE SPI CONTROL Functionality Available in SPI Control Mode Offset and Gain Correction SPI Control Functionality Global Control Functions Per Channel Functions Phase Adjustment PGA Gain Decimation GPIOx Pins Σ-Δ Reference Configuration Power Modes Sinc3 and Sinc5 Filters LDO Bypassing DIGITAL SPI SPI CRC—Checksum Protection (SPI Control Mode) SPI Read/Write Register Mode (SPI Control Mode) SPI SAR Diagnostic Mode (SPI Control Mode) Σ-Δ Data, ADC Mode SPI Software Reset RMS NOISE AND RESOLUTION HIGH RESOLUTION MODE LOW POWER MODE DIAGNOSTICS AND MONITORING SELF DIAGNOSTICS ERROR General Errors MCLK Switch Error (SPI Control Mode) Reset Detection Internal LDO Status ROM and Memory Map CRC Σ-Δ ADC Errors Reference Detect (SPI Control Mode) Overvoltage and Undervoltage Events Modulator Saturation Filter Saturation Output Saturation SPI Transmission Errors (SPI Control Mode) CRC Checksum Error SCLK Counter Invalid Read Invalid Write MONITORING USING THE AD7771 SAR ADC(SPI CONTROL MODE) Temperature Sensor Σ-Δ ADC DIAGNOSTICS (SPI CONTROL MODE) Σ-∆ OUTPUT DATA ADC CONVERSION OUTPUT—HEADER AND DATA CRC Header Error Header (SPI Control Mode) SAMPLE RATE CONVERTER (SRC) (SPI CONTROL MODE) SRC Bandwidth SRC Group Delay Settling Time DATA OUTPUT INTERFACE DOUT3 to DOUT0 Data Interface Standalone Mode Daisy-Chain Mode Minimum DCLKx Frequency SPI CALCULATING THE CRC CHECKSUM Σ-Δ CRC Checksum SPI Control Mode Checksum REGISTER SUMMARY REGISTER DETAILS CHANNEL 0 CONFIGURATION REGISTER CHANNEL 1 CONFIGURATION REGISTER CHANNEL 2 CONFIGURATION REGISTER CHANNEL 3 CONFIGURATION REGISTER CHANNEL 4 CONFIGURATION REGISTER CHANNEL 5 CONFIGURATION REGISTER CHANNEL 6 CONFIGURATION REGISTER CHANNEL 7 CONFIGURATION REGISTER DISABLE CLOCKS TO ADC CHANNEL REGISTER CHANNEL 0 SYNC OFFSET REGISTER CHANNEL 1 SYNC OFFSET REGISTER CHANNEL 2 SYNC OFFSET REGISTER CHANNEL 3 SYNC OFFSET REGISTER CHANNEL 4 SYNC OFFSET REGISTER CHANNEL 5 SYNC OFFSET REGISTER CHANNEL 6 SYNC OFFSET REGISTER CHANNEL 7 SYNC OFFSET REGISTER GENERAL USER CONFIGURATION 1 REGISTER GENERAL USER CONFIGURATION 2 REGISTER GENERAL USER CONFIGURATION 3 REGISTER DATA OUTPUT FORMAT REGISTER MAIN ADC METER AND REFERENCE MUX CONTROL REGISTER GLOBAL DIAGNOSTICS MUX REGISTER GPIO CONFIGURATION REGISTER GPIO DATA REGISTER BUFFER CONFIGURATION 1 REGISTER BUFFER CONFIGURATION 2 REGISTER CHANNEL 0 OFFSET UPPER BYTE REGISTER CHANNEL 0 OFFSET MIDDLE BYTE REGISTER CHANNEL 0 OFFSET LOWER BYTE REGISTER CHANNEL 0 GAIN UPPER BYTE REGISTER CHANNEL 0 GAIN MIDDLE BYTE REGISTER CHANNEL 0 GAIN LOWER BYTE REGISTER CHANNEL 1 OFFSET UPPER BYTE REGISTER CHANNEL 1 OFFSET MIDDLE BYTE REGISTER CHANNEL 1 OFFSET LOWER BYTE REGISTER CHANNEL 1 GAIN UPPER BYTE REGISTER CHANNEL 1 GAIN MIDDLE BYTE REGISTER CHANNEL 1 GAIN LOWER BYTE REGISTER CHANNEL 2 OFFSET UPPER BYTE REGISTER CHANNEL 2 OFFSET MIDDLE BYTE REGISTER CHANNEL 2 OFFSET LOWER BYTE REGISTER CHANNEL 2 GAIN UPPER BYTE REGISTER CHANNEL 2 GAIN MIDDLE BYTE REGISTER CHANNEL 2 GAIN LOWER BYTE REGISTER CHANNEL 3 OFFSET UPPER BYTE REGISTER CHANNEL 3 OFFSET MIDDLE BYTE REGISTER CHANNEL 3 OFFSET LOWER BYTE REGISTER CHANNEL 3 GAIN UPPER BYTE REGISTER CHANNEL 3 GAIN MIDDLE BYTE REGISTER CHANNEL 3 GAIN LOWER BYTE REGISTER CHANNEL 4 OFFSET UPPER BYTE REGISTER CHANNEL 4 OFFSET MIDDLE BYTE REGISTER CHANNEL 4 OFFSET LOWER BYTE REGISTER CHANNEL 4 GAIN UPPER BYTE REGISTER CHANNEL 4 GAIN MIDDLE BYTE REGISTER CHANNEL 4 GAIN LOWER BYTE REGISTER CHANNEL 5 OFFSET UPPER BYTE REGISTER CHANNEL 5 OFFSET MIDDLE BYTE REGISTER CHANNEL 5 OFFSET LOWER BYTE REGISTER CHANNEL 5 GAIN UPPER BYTE REGISTER CHANNEL 5 GAIN MIDDLE BYTE REGISTER CHANNEL 5 GAIN LOWER BYTE REGISTER CHANNEL 6 OFFSET UPPER BYTE REGISTER CHANNEL 6 OFFSET MIDDLE BYTE REGISTER CHANNEL 6 OFFSET LOWER BYTE REGISTER CHANNEL 6 GAIN UPPER BYTE REGISTER CHANNEL 6 GAIN MIDDLE BYTE REGISTER CHANNEL 6 GAIN LOWER BYTE REGISTER CHANNEL 7 OFFSET UPPER BYTE REGISTER CHANNEL 7 OFFSET MIDDLE BYTE REGISTER CHANNEL 7 OFFSET LOWER BYTE REGISTER CHANNEL 7 GAIN UPPER BYTE REGISTER CHANNEL 7 GAIN MIDDLE BYTE REGISTER CHANNEL 7 GAIN LOWER BYTE REGISTER CHANNEL 0 STATUS REGISTER CHANNEL 1 STATUS REGISTER CHANNEL 2 STATUS REGISTER CHANNEL 3 STATUS REGISTER CHANNEL 4 STATUS REGISTER CHANNEL 5 STATUS REGISTER CHANNEL 6 STATUS REGISTER CHANNEL 7 STATUS REGISTER CHANNEL 0/CHANNEL 1 DSP ERRORS REGISTER CHANNEL 2/CHANNEL 3 DSP ERRORS REGISTER CHANNEL 4/CHANNEL 5 DSP ERRORS REGISTER CHANNEL 6/CHANNEL 7 DSP ERRORS REGISTER CHANNEL 0 TO CHANNEL 7 ERROR REGISTER ENABLE REGISTER GENERAL ERRORS REGISTER 1 GENERAL ERRORS REGISTER 1 ENABLE GENERAL ERRORS REGISTER 2 GENERAL ERRORS REGISTER 2 ENABLE ERROR STATUS REGISTER 1 ERROR STATUS REGISTER 2 ERROR STATUS REGISTER 3 DECIMATION RATE (N) MSB REGISTER DECIMATION RATE (N) LSB REGISTER DECIMATION RATE (IF) MSB REGISTER DECIMATION RATE (IF) LSB REGISTER SRC LOAD SOURCE AND LOAD UPDATE REGISTER OUTLINE DIMENSIONS ORDERING GUIDE