Datasheet MCP6481, MCP6482, MCP6484 (Microchip) - 8
| Hersteller | Microchip |
| Beschreibung | The Microchip’s MCP6481 operational amplifiers (op amps) has low input bias current (150 pA, typical at 125°C) and rail-to-rail input and output operation |
| Seiten / Seite | 50 / 8 — MCP6481/2/4. Note:. 1,000. 105. 100. PSRR. (dB). ltage Density. Hz). ¥ … |
| Dateiformat / Größe | PDF / 1.9 Mb |
| Dokumentensprache | Englisch |
MCP6481/2/4. Note:. 1,000. 105. 100. PSRR. (dB). ltage Density. Hz). ¥ 100. (nV/. CMRR @ V. = 5.5V. MRR, PSRR. oise V. @ V. = 2 2. . V. Input. -50. -25. 125
Modelllinie für dieses Datenblatt
Textversion des Dokuments
MCP6481/2/4 Note:
Unless otherwise indicated, T A = +25°C, VDD = +2.2V to +5.5V, VSS = GND, VCM = VDD/2, VOUT VDD/2, VL = VDD/2, RL = 10 kto VL and CL = 20 pF.
1,000 105 100 PSRR 95 (dB) 90 ltage Density Hz) o ¥ 100 85 (nV/ 80 CMRR @ V = 5.5V MRR, PSRR DD oise V @ V = 2 2 . V C 2V DD N 75 70 Input 10 65 -50 -25 0 25 50 75 100 125 1.E-1 1.E+0 1.E+1 1.E+2 0.1 1 10 100 1.E+3 1k 1.E+4 1.E+5 1.E+6 10k 100k 1M Frequency (Hz) Temperature (°C) FIGURE 2-7:
Input Noise Voltage Density
FIGURE 2-10:
CMRR, PSRR vs. Ambient vs. Frequency. Temperature.
1000 30 1n V = 5.5 V 25 DD 100 100p Currents 20 Input Bias Current 10 10p Hz) ¥ 15 (A) (nV/ 1 1p 10 ltage Noise Density s and Offset o V f = 10 kHz 5 0.1p V = 5.5 V 0.1 DD Input Offset Current Input 0 Input Bia 0.01 0.01p 5 -0.5 0.0 0.5 1.0 1.5 2.0 2.5 3.0 3.5 4.0 4.5 5.0 5.5 6.0 25 35 45 55 65 75 85 95 105 11 125 Common Mode Input Voltage (V) Ambient Temperature (°C) FIGURE 2-8:
Input Noise Voltage Density
FIGURE 2-11:
Input Bias, Offset Currents vs. Common Mode Input Voltage. vs. Ambient Temperature.
100 250 90 Representative Part V = 5.5 V 200 DD 80 PSRR+ T = +125°C 150 A 70 60 CMRR 100 50 Bias Current (pA) 50 t T = +85°C PSRR- u A u 40 CMRR, PSRR (dB) Inp 0 30 T = +25°C A -50 20 1.00E+01 1.00E+02 1.00E+03 1.00E+04 1.00E+05 1.00E+06 10 100 1k 10k 100k 1M 0.0 0.5 1.0 1.5 2.0 2.5 3.0 3.5 4.0 4.5 5.0 5.5 Frequency (Hz) Common Mode Input Voltage (V) FIGURE 2-9:
CMRR, PSRR vs.
FIGURE 2-12:
Input Bias Current vs. Frequency. Common Mode Input Voltage. DS20002322C-page 8 2012-2013 Microchip Technology Inc. Document Outline Package Types Typical Application 1.0 Electrical Characteristics 1.1 Absolute Maximum Ratings 1.2 Specifications TABLE 1-1: DC Electrical Specifications TABLE 1-2: AC Electrical Specifications TABLE 1-3: Temperature Specifications 1.3 Test Circuits FIGURE 1-1: AC and DC Test Circuit for Most Specifications. 2.0 Typical Performance Curves FIGURE 2-1: Input Offset Voltage. FIGURE 2-2: Input Offset Voltage Drift. FIGURE 2-3: Input Offset Voltage vs. Common Mode Input Voltage. FIGURE 2-4: Input Offset Voltage vs. Common Mode Input Voltage. FIGURE 2-5: Input Offset Voltage vs. Output Voltage. FIGURE 2-6: Input Offset Voltage vs. Power Supply Voltage. FIGURE 2-7: Input Noise Voltage Density vs. Frequency. FIGURE 2-8: Input Noise Voltage Density vs. Common Mode Input Voltage. FIGURE 2-9: CMRR, PSRR vs. Frequency. FIGURE 2-10: CMRR, PSRR vs. Ambient Temperature. FIGURE 2-11: Input Bias, Offset Currents vs. Ambient Temperature. FIGURE 2-12: Input Bias Current vs. Common Mode Input Voltage. FIGURE 2-13: Quiescent Current vs. Ambient Temperature. FIGURE 2-14: Quiescent Current vs. Common Mode Input Voltage. FIGURE 2-15: Quiescent Current vs. Common Mode Input Voltage. FIGURE 2-16: Quiescent Current vs. Power Supply Voltage. FIGURE 2-17: Open-Loop Gain, Phase vs. Frequency. FIGURE 2-18: DC Open-Loop Gain vs. Ambient Temperature. FIGURE 2-19: Gain Bandwidth Product, Phase Margin vs. Ambient Temperature. FIGURE 2-20: Gain Bandwidth Product, Phase Margin vs. Ambient Temperature. FIGURE 2-21: Output Short Circuit Current vs. Power Supply Voltage. FIGURE 2-22: Output Voltage Swing vs. Frequency. FIGURE 2-23: Output Voltage Headroom vs. Output Current. FIGURE 2-24: Output Voltage Headroom vs. Output Current. FIGURE 2-25: Output Voltage Headroom vs. Ambient Temperature. FIGURE 2-26: Output Voltage Headroom vs. Ambient Temperature. FIGURE 2-27: Slew Rate vs. Ambient Temperature. FIGURE 2-28: Small Signal Non-Inverting Pulse Response. FIGURE 2-29: Small Signal Inverting Pulse Response. FIGURE 2-30: Large Signal Non-Inverting Pulse Response. FIGURE 2-31: Large Signal Inverting Pulse Response. FIGURE 2-32: The MCP6481/2/4 Shows No Phase Reversal. FIGURE 2-33: Closed Loop Output Impedance vs. Frequency. FIGURE 2-34: Measured Input Current vs. Input Voltage (below VSS). FIGURE 2-35: Channel-to-Channel Separation vs. Frequency (MCP6482/4 only). 3.0 Pin Descriptions TABLE 3-1: Pin Function Table 3.1 Analog Outputs 3.2 Analog Inputs 3.3 Power Supply Pins 3.4 Exposed Thermal Pad (EP) 4.0 Application Information 4.1 Inputs FIGURE 4-1: Simplified Analog Input ESD Structures. FIGURE 4-2: Protecting the Analog Inputs. FIGURE 4-3: Protecting the Analog Inputs. 4.2 Rail-to-Rail Output 4.3 Capacitive Loads FIGURE 4-4: Output Resistor, RISO Stabilizes Large Capacitive Loads. FIGURE 4-5: Recommended RISO Values for Capacitive Loads. 4.4 Supply Bypass 4.5 Unused Op Amps FIGURE 4-6: Unused Op Amps. 4.6 PCB Surface Leakage FIGURE 4-7: Example Guard Ring Layout for Inverting Gain. 4.7 Application Circuits FIGURE 4-8: Photovoltaic Mode Detector. FIGURE 4-9: Photoconductive Mode Detector. FIGURE 4-10: Second-Order, Low-Pass Butterworth Filter with Sallen-Key Topology. FIGURE 4-11: Second-Order, Low-Pass Butterworth Filter with Multiple-Feedback Topology. FIGURE 4-12: pH Electrode Amplifier. 5.0 Design Aids 5.1 SPICE Macro Model 5.2 FilterLab Software 5.3 MAPS (Microchip Advanced Part Selector) 5.4 Analog Demonstration and Evaluation Boards 5.5 Application Notes 6.0 Packaging Information 6.1 Package Marking Information Appendix A: Revision History Product Identification System Trademarks Worldwide Sales and Service
Unless otherwise indicated, T A = +25°C, VDD = +2.2V to +5.5V, VSS = GND, VCM = VDD/2, VOUT VDD/2, VL = VDD/2, RL = 10 kto VL and CL = 20 pF.
1,000 105 100 PSRR 95 (dB) 90 ltage Density Hz) o ¥ 100 85 (nV/ 80 CMRR @ V = 5.5V MRR, PSRR DD oise V @ V = 2 2 . V C 2V DD N 75 70 Input 10 65 -50 -25 0 25 50 75 100 125 1.E-1 1.E+0 1.E+1 1.E+2 0.1 1 10 100 1.E+3 1k 1.E+4 1.E+5 1.E+6 10k 100k 1M Frequency (Hz) Temperature (°C) FIGURE 2-7:
Input Noise Voltage Density
FIGURE 2-10:
CMRR, PSRR vs. Ambient vs. Frequency. Temperature.
1000 30 1n V = 5.5 V 25 DD 100 100p Currents 20 Input Bias Current 10 10p Hz) ¥ 15 (A) (nV/ 1 1p 10 ltage Noise Density s and Offset o V f = 10 kHz 5 0.1p V = 5.5 V 0.1 DD Input Offset Current Input 0 Input Bia 0.01 0.01p 5 -0.5 0.0 0.5 1.0 1.5 2.0 2.5 3.0 3.5 4.0 4.5 5.0 5.5 6.0 25 35 45 55 65 75 85 95 105 11 125 Common Mode Input Voltage (V) Ambient Temperature (°C) FIGURE 2-8:
Input Noise Voltage Density
FIGURE 2-11:
Input Bias, Offset Currents vs. Common Mode Input Voltage. vs. Ambient Temperature.
100 250 90 Representative Part V = 5.5 V 200 DD 80 PSRR+ T = +125°C 150 A 70 60 CMRR 100 50 Bias Current (pA) 50 t T = +85°C PSRR- u A u 40 CMRR, PSRR (dB) Inp 0 30 T = +25°C A -50 20 1.00E+01 1.00E+02 1.00E+03 1.00E+04 1.00E+05 1.00E+06 10 100 1k 10k 100k 1M 0.0 0.5 1.0 1.5 2.0 2.5 3.0 3.5 4.0 4.5 5.0 5.5 Frequency (Hz) Common Mode Input Voltage (V) FIGURE 2-9:
CMRR, PSRR vs.
FIGURE 2-12:
Input Bias Current vs. Frequency. Common Mode Input Voltage. DS20002322C-page 8 2012-2013 Microchip Technology Inc. Document Outline Package Types Typical Application 1.0 Electrical Characteristics 1.1 Absolute Maximum Ratings 1.2 Specifications TABLE 1-1: DC Electrical Specifications TABLE 1-2: AC Electrical Specifications TABLE 1-3: Temperature Specifications 1.3 Test Circuits FIGURE 1-1: AC and DC Test Circuit for Most Specifications. 2.0 Typical Performance Curves FIGURE 2-1: Input Offset Voltage. FIGURE 2-2: Input Offset Voltage Drift. FIGURE 2-3: Input Offset Voltage vs. Common Mode Input Voltage. FIGURE 2-4: Input Offset Voltage vs. Common Mode Input Voltage. FIGURE 2-5: Input Offset Voltage vs. Output Voltage. FIGURE 2-6: Input Offset Voltage vs. Power Supply Voltage. FIGURE 2-7: Input Noise Voltage Density vs. Frequency. FIGURE 2-8: Input Noise Voltage Density vs. Common Mode Input Voltage. FIGURE 2-9: CMRR, PSRR vs. Frequency. FIGURE 2-10: CMRR, PSRR vs. Ambient Temperature. FIGURE 2-11: Input Bias, Offset Currents vs. Ambient Temperature. FIGURE 2-12: Input Bias Current vs. Common Mode Input Voltage. FIGURE 2-13: Quiescent Current vs. Ambient Temperature. FIGURE 2-14: Quiescent Current vs. Common Mode Input Voltage. FIGURE 2-15: Quiescent Current vs. Common Mode Input Voltage. FIGURE 2-16: Quiescent Current vs. Power Supply Voltage. FIGURE 2-17: Open-Loop Gain, Phase vs. Frequency. FIGURE 2-18: DC Open-Loop Gain vs. Ambient Temperature. FIGURE 2-19: Gain Bandwidth Product, Phase Margin vs. Ambient Temperature. FIGURE 2-20: Gain Bandwidth Product, Phase Margin vs. Ambient Temperature. FIGURE 2-21: Output Short Circuit Current vs. Power Supply Voltage. FIGURE 2-22: Output Voltage Swing vs. Frequency. FIGURE 2-23: Output Voltage Headroom vs. Output Current. FIGURE 2-24: Output Voltage Headroom vs. Output Current. FIGURE 2-25: Output Voltage Headroom vs. Ambient Temperature. FIGURE 2-26: Output Voltage Headroom vs. Ambient Temperature. FIGURE 2-27: Slew Rate vs. Ambient Temperature. FIGURE 2-28: Small Signal Non-Inverting Pulse Response. FIGURE 2-29: Small Signal Inverting Pulse Response. FIGURE 2-30: Large Signal Non-Inverting Pulse Response. FIGURE 2-31: Large Signal Inverting Pulse Response. FIGURE 2-32: The MCP6481/2/4 Shows No Phase Reversal. FIGURE 2-33: Closed Loop Output Impedance vs. Frequency. FIGURE 2-34: Measured Input Current vs. Input Voltage (below VSS). FIGURE 2-35: Channel-to-Channel Separation vs. Frequency (MCP6482/4 only). 3.0 Pin Descriptions TABLE 3-1: Pin Function Table 3.1 Analog Outputs 3.2 Analog Inputs 3.3 Power Supply Pins 3.4 Exposed Thermal Pad (EP) 4.0 Application Information 4.1 Inputs FIGURE 4-1: Simplified Analog Input ESD Structures. FIGURE 4-2: Protecting the Analog Inputs. FIGURE 4-3: Protecting the Analog Inputs. 4.2 Rail-to-Rail Output 4.3 Capacitive Loads FIGURE 4-4: Output Resistor, RISO Stabilizes Large Capacitive Loads. FIGURE 4-5: Recommended RISO Values for Capacitive Loads. 4.4 Supply Bypass 4.5 Unused Op Amps FIGURE 4-6: Unused Op Amps. 4.6 PCB Surface Leakage FIGURE 4-7: Example Guard Ring Layout for Inverting Gain. 4.7 Application Circuits FIGURE 4-8: Photovoltaic Mode Detector. FIGURE 4-9: Photoconductive Mode Detector. FIGURE 4-10: Second-Order, Low-Pass Butterworth Filter with Sallen-Key Topology. FIGURE 4-11: Second-Order, Low-Pass Butterworth Filter with Multiple-Feedback Topology. FIGURE 4-12: pH Electrode Amplifier. 5.0 Design Aids 5.1 SPICE Macro Model 5.2 FilterLab Software 5.3 MAPS (Microchip Advanced Part Selector) 5.4 Analog Demonstration and Evaluation Boards 5.5 Application Notes 6.0 Packaging Information 6.1 Package Marking Information Appendix A: Revision History Product Identification System Trademarks Worldwide Sales and Service