Datasheet MCP601, MCP601R, MCP602, MCP603, MCP604 (Microchip) - 6
| Hersteller | Microchip |
| Beschreibung | MCP601 operational amplifier (op amp) has a gain bandwidth product of 2.8 MHz with low typical operating current of 230 uA and an offset voltage that is less than 2 mV |
| Seiten / Seite | 34 / 6 — MCP601/1R/2/3/4. Note:. 16%. 18%. 1200 Samples. 14%. 16% TA = –40 to … |
| Dateiformat / Größe | PDF / 600 Kb |
| Dokumentensprache | Englisch |
MCP601/1R/2/3/4. Note:. 16%. 18%. 1200 Samples. 14%. 16% TA = –40 to +125°C. 12%. 14% 12%. 10%. Occurrences. age of Occurrences. rcentage of
Modelllinie für dieses Datenblatt
- MCP601-E/P MCP601-E/SN MCP601-E/ST MCP601-I/P MCP601-I/SN MCP601-I/ST MCP601RT-E/OT MCP601RT-I/OT MCP601T-E/OT MCP601T-E/OTVAO MCP601T-E/SN MCP601T-E/ST MCP601T-I/OT MCP601T-I/OTG MCP601T-I/SN MCP601T-I/ST
- MCP602-E/P MCP602-E/SN MCP602-E/ST MCP602-I/P MCP602-I/SN MCP602-I/ST MCP602T-E/SN MCP602T-E/ST MCP602T-E/STVAO MCP602T-I/SN MCP602T-I/ST
- MCP603-E/P MCP603-E/SN MCP603-E/ST MCP603-I/P MCP603-I/SN MCP603-I/ST MCP603T-E/CH MCP603T-E/SN MCP603T-E/ST MCP603T-I/CH MCP603T-I/SN MCP603T-I/ST
- MCP604-E/P MCP604-E/SL MCP604-E/ST MCP604-E/STVAO MCP604-I/P MCP604-I/SL MCP604-I/ST MCP6041-E/MS MCP6041-E/P MCP6041-E/SN MCP6041-E/SNVAO MCP6041-I/MS MCP6041-I/P MCP6041-I/SN MCP6041T-E/MS MCP6041T-E/OT MCP6041T-E/OTVAO MCP6041T-E/SN MCP6041T-I/MS MCP6041T-I/OT MCP6041T-I/OTG MCP6041T-I/SN MCP6042-E/MS MCP6042-E/MSVAO MCP6042-E/P MCP6042-E/SN MCP6042-E/SNVAO MCP6042-I/MS MCP6042-I/P MCP6042-I/SN MCP6042T-E/MS MCP6042T-E/MSVAO MCP6042T-E/SN MCP6042T-E/SNVAO MCP6042T-I/MS MCP6042T-I/SN MCP6043-E/MS MCP6043-E/P MCP6043-E/SN MCP6043-I/MS MCP6043-I/P MCP6043-I/SN MCP6043T-E/CH MCP6043T-E/MS MCP6043T-E/SN MCP6043T-I/CH MCP6043T-I/MS MCP6043T-I/SN MCP6044-E/P MCP6044-E/SL MCP6044-E/ST MCP6044-I/P MCP6044-I/SL MCP6044-I/ST MCP6044T-E/SL MCP6044T-E/ST MCP6044T-E/STVAO MCP6044T-I/SL MCP6044T-I/ST MCP604T-E/SL MCP604T-E/ST MCP604T-E/STVAO MCP604T-I/SL MCP604T-I/ST
Textversion des Dokuments
MCP601/1R/2/3/4 Note:
Unless otherwise indicated, TA = +25°C, VDD = +2.7V to +5.5V, VSS = GND, VCM = VDD/2, VOUT ≈ VDD/2, VL = VDD/2, RL = 100 kΩ to VL, CL = 50 pF and CS is tied low.
16% 18% 1200 Samples 1200 Samples 14% 16% TA = –40 to +125°C 12% 14% 12% 10% 10% Occurrences 8% 8% 6% 6% age of Occurrences 4% 4% rcentage of 2% e 2% P Percent 0% 0% -2.0 -1.6 -1.2 -0.8 -0.4 0.0 0.4 0.8 1.2 1.6 2.0 -10 -8 -6 -4 -2 0 2 4 6 8 10 Input Offset Voltage (mV) Input Offset Voltage Drift (µV/°C) FIGURE 2-7:
Input Offset Voltage.
FIGURE 2-10:
Input Offset Voltage Drift.
0.5 100 0.4 V) m 0.3 VDD = 5.5V 95 e ( 0.2 B) d 0.1 90 PSRR V 0.0 DD = 2.7V -0.1 set Voltag , PSRR ( 85 R CMRR -0.2 R Off -0.3 CM 80 -0.4 Input -0.5 75 -50 -25 0 25 50 75 100 125 -50 -25 0 25 50 75 100 125 Ambient Temperature (°C) Ambient Temperature (°C) FIGURE 2-8:
Input Offset Voltage vs.
FIGURE 2-11:
CMRR, PSRR vs. Temperature. Temperature.
800 800 700 VDD = 2.7V 700 VDD = 5.5V V) V) µ 600 µ 600 TA = –40°C e ( e ( g 500 T T A = –40°C g 500 A = +25°C ta 400 T ta T A = +25°C 400 A = +85°C Vol 300 T Vol A = +85°C 300 et 200 et 200 ffs ffs 100 O 100 O TA = +125°C 0 TA = +125°C 0 Input -100 Input -100 -200 -200 .4 .2 0 2 4 6 8 0 2 4 6 8 0 .5 0 5 0 5 0 5 0 5 0 5 0 -0 -0 0. 0. 0. 0. 0. 1. 1. 1. 1. 1. 2. -0 0. 0. 1. 1. 2. 2. 3. 3. 4. 4. 5. Common Mode Input Voltage (V) Common Mode Input Voltage (V) FIGURE 2-9:
Input Offset Voltage vs.
FIGURE 2-12:
Input Offset Voltage vs. Common Mode Input Voltage with VDD = 2.7V. Common Mode Input Voltage with VDD = 5.5V. DS21314G-page 6 © 2007 Microchip Technology Inc. Document Outline 1.0 Electrical Characteristics FIGURE 1-1: MCP603 Chip Select (CS) Timing Diagram. 1.1 Test Circuits FIGURE 1-2: AC and DC Test Circuit for Most Non-Inverting Gain Conditions. FIGURE 1-3: AC and DC Test Circuit for Most Inverting Gain Conditions. 2.0 Typical Performance Curves FIGURE 2-1: Open-Loop Gain, Phase vs. Frequency. FIGURE 2-2: Slew Rate vs. Temperature. FIGURE 2-3: Gain Bandwidth Product, Phase Margin vs. Temperature. FIGURE 2-4: Quiescent Current vs. Supply Voltage. FIGURE 2-5: Quiescent Current vs. Temperature. FIGURE 2-6: Input Noise Voltage Density vs. Frequency. FIGURE 2-7: Input Offset Voltage. FIGURE 2-8: Input Offset Voltage vs. Temperature. FIGURE 2-9: Input Offset Voltage vs. Common Mode Input Voltage with VDD = 2.7V. FIGURE 2-10: Input Offset Voltage Drift. FIGURE 2-11: CMRR, PSRR vs. Temperature. FIGURE 2-12: Input Offset Voltage vs. Common Mode Input Voltage with VDD = 5.5V. FIGURE 2-13: Channel-to-Channel Separation vs. Frequency. FIGURE 2-14: Input Bias Current, Input Offset Current vs. Ambient Temperature. FIGURE 2-15: DC Open-Loop Gain vs. Load Resistance. FIGURE 2-16: CMRR, PSRR vs. Frequency. FIGURE 2-17: Input Bias Current, Input Offset Current vs. Common Mode Input Voltage. FIGURE 2-18: DC Open-Loop Gain vs. Supply Voltage. FIGURE 2-19: Gain Bandwidth Product, Phase Margin vs. Load Resistance. FIGURE 2-20: Output Voltage Headroom vs. Output Current. FIGURE 2-21: Maximum Output Voltage Swing vs. Frequency. FIGURE 2-22: DC Open-Loop Gain vs. Temperature. FIGURE 2-23: Output Voltage Headroom vs. Temperature. FIGURE 2-24: Output Short-Circuit Current vs. Supply Voltage. FIGURE 2-25: Large Signal Non-Inverting Pulse Response. FIGURE 2-26: Small Signal Non-Inverting Pulse Response. FIGURE 2-27: Chip Select Timing (MCP603). FIGURE 2-28: Large Signal Inverting Pulse Response. FIGURE 2-29: Small Signal Inverting Pulse Response. FIGURE 2-30: Quiescent Current Through VSS vs. Chip Select Voltage (MCP603). FIGURE 2-31: Chip Select Pin Input Current vs. Chip Select Voltage. FIGURE 2-32: Hysteresis of Chip Select’s Internal Switch. FIGURE 2-33: The MCP601/1R/2/3/4 family of op amps shows no phase reversal under input overdrive. FIGURE 2-34: Measured Input Current vs. Input Voltage (below VSS). 3.0 Pin Descriptions TABLE 3-1: Pin Function Table For Single Op Amps TABLE 3-2: Pin Function Table For Dual And Quad Op Amps 3.1 Analog Outputs 3.2 Analog Inputs 3.3 Chip Select Digital Input 3.4 Power Supply Pins 4.0 Applications Information 4.1 Inputs FIGURE 4-1: Simplified Analog Input ESD Structures. FIGURE 4-2: Protecting the Analog Inputs. FIGURE 4-3: Unity Gain Buffer has a Limited VOUT Range. 4.2 Rail-to-Rail Output 4.3 MCP603 Chip Select 4.4 Capacitive Loads FIGURE 4-4: Output resistor RISO stabilizes large capacitive loads. FIGURE 4-5: Recommended RISO values for capacitive loads. 4.5 Supply Bypass 4.6 Unused Op Amps FIGURE 4-6: Unused Op Amps. 4.7 PCB Surface Leakage FIGURE 4-7: Example Guard Ring layout. 4.8 Typical Applications FIGURE 4-8: Second-Order, Low-Pass Sallen-Key Filter. FIGURE 4-9: Second-Order, Low-Pass Multiple-Feedback Filter. FIGURE 4-10: Three-Op Amp Instrumentation Amplifier. FIGURE 4-11: Two-Op Amp Instrumentation Amplifier. FIGURE 4-12: Photovoltaic Mode Detector. FIGURE 4-13: Photoconductive Mode Detector. 5.0 Design Aids 5.1 SPICE Macro Model 5.2 FilterLab® Software 5.3 Mindi™ Simulatior Tool 5.4 MAPS (Microchip Advanced Part Selector) 5.5 Analog Demonstration and Evaluation Boards 5.6 Application Notes 6.0 Packaging Information 6.1 Package Marking Information
Unless otherwise indicated, TA = +25°C, VDD = +2.7V to +5.5V, VSS = GND, VCM = VDD/2, VOUT ≈ VDD/2, VL = VDD/2, RL = 100 kΩ to VL, CL = 50 pF and CS is tied low.
16% 18% 1200 Samples 1200 Samples 14% 16% TA = –40 to +125°C 12% 14% 12% 10% 10% Occurrences 8% 8% 6% 6% age of Occurrences 4% 4% rcentage of 2% e 2% P Percent 0% 0% -2.0 -1.6 -1.2 -0.8 -0.4 0.0 0.4 0.8 1.2 1.6 2.0 -10 -8 -6 -4 -2 0 2 4 6 8 10 Input Offset Voltage (mV) Input Offset Voltage Drift (µV/°C) FIGURE 2-7:
Input Offset Voltage.
FIGURE 2-10:
Input Offset Voltage Drift.
0.5 100 0.4 V) m 0.3 VDD = 5.5V 95 e ( 0.2 B) d 0.1 90 PSRR V 0.0 DD = 2.7V -0.1 set Voltag , PSRR ( 85 R CMRR -0.2 R Off -0.3 CM 80 -0.4 Input -0.5 75 -50 -25 0 25 50 75 100 125 -50 -25 0 25 50 75 100 125 Ambient Temperature (°C) Ambient Temperature (°C) FIGURE 2-8:
Input Offset Voltage vs.
FIGURE 2-11:
CMRR, PSRR vs. Temperature. Temperature.
800 800 700 VDD = 2.7V 700 VDD = 5.5V V) V) µ 600 µ 600 TA = –40°C e ( e ( g 500 T T A = –40°C g 500 A = +25°C ta 400 T ta T A = +25°C 400 A = +85°C Vol 300 T Vol A = +85°C 300 et 200 et 200 ffs ffs 100 O 100 O TA = +125°C 0 TA = +125°C 0 Input -100 Input -100 -200 -200 .4 .2 0 2 4 6 8 0 2 4 6 8 0 .5 0 5 0 5 0 5 0 5 0 5 0 -0 -0 0. 0. 0. 0. 0. 1. 1. 1. 1. 1. 2. -0 0. 0. 1. 1. 2. 2. 3. 3. 4. 4. 5. Common Mode Input Voltage (V) Common Mode Input Voltage (V) FIGURE 2-9:
Input Offset Voltage vs.
FIGURE 2-12:
Input Offset Voltage vs. Common Mode Input Voltage with VDD = 2.7V. Common Mode Input Voltage with VDD = 5.5V. DS21314G-page 6 © 2007 Microchip Technology Inc. Document Outline 1.0 Electrical Characteristics FIGURE 1-1: MCP603 Chip Select (CS) Timing Diagram. 1.1 Test Circuits FIGURE 1-2: AC and DC Test Circuit for Most Non-Inverting Gain Conditions. FIGURE 1-3: AC and DC Test Circuit for Most Inverting Gain Conditions. 2.0 Typical Performance Curves FIGURE 2-1: Open-Loop Gain, Phase vs. Frequency. FIGURE 2-2: Slew Rate vs. Temperature. FIGURE 2-3: Gain Bandwidth Product, Phase Margin vs. Temperature. FIGURE 2-4: Quiescent Current vs. Supply Voltage. FIGURE 2-5: Quiescent Current vs. Temperature. FIGURE 2-6: Input Noise Voltage Density vs. Frequency. FIGURE 2-7: Input Offset Voltage. FIGURE 2-8: Input Offset Voltage vs. Temperature. FIGURE 2-9: Input Offset Voltage vs. Common Mode Input Voltage with VDD = 2.7V. FIGURE 2-10: Input Offset Voltage Drift. FIGURE 2-11: CMRR, PSRR vs. Temperature. FIGURE 2-12: Input Offset Voltage vs. Common Mode Input Voltage with VDD = 5.5V. FIGURE 2-13: Channel-to-Channel Separation vs. Frequency. FIGURE 2-14: Input Bias Current, Input Offset Current vs. Ambient Temperature. FIGURE 2-15: DC Open-Loop Gain vs. Load Resistance. FIGURE 2-16: CMRR, PSRR vs. Frequency. FIGURE 2-17: Input Bias Current, Input Offset Current vs. Common Mode Input Voltage. FIGURE 2-18: DC Open-Loop Gain vs. Supply Voltage. FIGURE 2-19: Gain Bandwidth Product, Phase Margin vs. Load Resistance. FIGURE 2-20: Output Voltage Headroom vs. Output Current. FIGURE 2-21: Maximum Output Voltage Swing vs. Frequency. FIGURE 2-22: DC Open-Loop Gain vs. Temperature. FIGURE 2-23: Output Voltage Headroom vs. Temperature. FIGURE 2-24: Output Short-Circuit Current vs. Supply Voltage. FIGURE 2-25: Large Signal Non-Inverting Pulse Response. FIGURE 2-26: Small Signal Non-Inverting Pulse Response. FIGURE 2-27: Chip Select Timing (MCP603). FIGURE 2-28: Large Signal Inverting Pulse Response. FIGURE 2-29: Small Signal Inverting Pulse Response. FIGURE 2-30: Quiescent Current Through VSS vs. Chip Select Voltage (MCP603). FIGURE 2-31: Chip Select Pin Input Current vs. Chip Select Voltage. FIGURE 2-32: Hysteresis of Chip Select’s Internal Switch. FIGURE 2-33: The MCP601/1R/2/3/4 family of op amps shows no phase reversal under input overdrive. FIGURE 2-34: Measured Input Current vs. Input Voltage (below VSS). 3.0 Pin Descriptions TABLE 3-1: Pin Function Table For Single Op Amps TABLE 3-2: Pin Function Table For Dual And Quad Op Amps 3.1 Analog Outputs 3.2 Analog Inputs 3.3 Chip Select Digital Input 3.4 Power Supply Pins 4.0 Applications Information 4.1 Inputs FIGURE 4-1: Simplified Analog Input ESD Structures. FIGURE 4-2: Protecting the Analog Inputs. FIGURE 4-3: Unity Gain Buffer has a Limited VOUT Range. 4.2 Rail-to-Rail Output 4.3 MCP603 Chip Select 4.4 Capacitive Loads FIGURE 4-4: Output resistor RISO stabilizes large capacitive loads. FIGURE 4-5: Recommended RISO values for capacitive loads. 4.5 Supply Bypass 4.6 Unused Op Amps FIGURE 4-6: Unused Op Amps. 4.7 PCB Surface Leakage FIGURE 4-7: Example Guard Ring layout. 4.8 Typical Applications FIGURE 4-8: Second-Order, Low-Pass Sallen-Key Filter. FIGURE 4-9: Second-Order, Low-Pass Multiple-Feedback Filter. FIGURE 4-10: Three-Op Amp Instrumentation Amplifier. FIGURE 4-11: Two-Op Amp Instrumentation Amplifier. FIGURE 4-12: Photovoltaic Mode Detector. FIGURE 4-13: Photoconductive Mode Detector. 5.0 Design Aids 5.1 SPICE Macro Model 5.2 FilterLab® Software 5.3 Mindi™ Simulatior Tool 5.4 MAPS (Microchip Advanced Part Selector) 5.5 Analog Demonstration and Evaluation Boards 5.6 Application Notes 6.0 Packaging Information 6.1 Package Marking Information