Datasheet LT1567 (Analog Devices) - 10

LT1567
U U W U APPLICATIO S I FOR ATIO
output from the INV block (Pin 7). These two outputs cause a high Q LC resonance in the hundreds of kHz in the maintain equal gain and 180º phase shift over a wide chip’s supplies or ground reference. This may impair filter frequency range. This feature permits choosing the signal performance at those frequencies. In stringent filter polarity in single ended applications, and also performs applications, a compact, carefully laid out printed circuit single ended to differential conversion. The latter property board with good ground plane makes a difference in both is useful as an antialiasing filter to drive standard mono- stopband rejection and distortion. Finally, equipment to lithic A/D converters having differential inputs, as illus- measure filter performance can itself introduce distortion trated on the first page of this data sheet. or noise. Checking for these limits with a wire in place of the filter is a prudent routine procedure.
Dealing with High Source Impedances Low Noise Differential Circuits
The voltage VIN in Figure 1, on the left side of R1, is the signal voltage that the filter sees. If a voltage source with The LT1567 is an optimum analog building for designing significant internal impedance drives the VIN node in single supply differential circuits to process low level Figure 1, then the filter input VIN may differ from the signals. Figure 3 shows a single ended to differential source’s open-circuit output, and the difference can be amplifier driving a 1st order differential RC filter. The complex, because the filter presents a complex imped- differential output of Figure 3 is a function of input (VIN) ance to VIN. A rule of thumb is that a source impedance is and the VREF voltage on Pin 5. (The range of the VREF negligibly “low” if it is much smaller than R1 at frequencies voltage on Pin 5 in Figures 3, 4 and 5 is the common mode of interest. Otherwise, the source impedance (resistive or input voltage range parameter under Electrical reactive) effectively adds to R1 and may change the signal Characteristics.)The graph of Figure 3 shows the differen- frequency response compared to that with a low source tial signal-to-noise ratio for a gain of 2 and a gain of 10. impedance. If the source is resistive and predictable, then Increasing the differential gain increases the differential it may be possible to design for it by reducing R1. signal-to-noise ratio. The equivalent input noise is equal to Unpredictable or nonresistive source impedances that are the output noise divided by the gain. For example, with a not much less than R1 should be buffered. gain equal to 2 (R2 = R1 = 200Ω) and a gain equal to 10 (R2 = 1k, R1 = 200Ω), the equivalent input noise is 4.59nV/
Construction and Instrumentation Cautions
√Hz and 2.04nV/√Hz respectively. The VREF voltage on Pin Electrically clean construction is important in applica- 5 can be set by a voltage divider or a reference voltage tions seeking the full dynamic range and bandwidth of the source. To maximize the unclipped LT1567 output swing, LT1567. Using the shortest possible wiring or printed- the DC output voltage should be set at V+/2. However, if circuit paths will minimize parasitic capacitance and VINDC (the input DC voltage) is within the range of VREF, inductance. High quality supply bypass capacitors of then VREF can be equal to VINDC. The input signal can also 0.1µF near the chip, connected to a ground plane, provide be AC coupled to the input resistor, R1, and VREF set to the good decoupling from a clean, low inductance power DC voltage of the circuit following the amplifier. For source. But several inches of wire (i.e., a few microhenrys example, VREF might be set to 1.2V to bias the input of an of inductance) from the power supplies, unless decoupled I and Q modulator used in broadband communication by substantial capacitance (≥10µF) near the chip, can systems. 1567fa 10