MIC7300 Micrel Application Information Output stage power (P ) is the product of the output stage O voltage drop (V ) and the output (load) current (I ). Input Common-Mode Voltage DROP OUT Total on-chip power dissipation is: The MIC7300 tolerates input overdrive by at least 300mV P = P + P beyond either rail without producing phase inversion. D S O P = V I + V I If the absolute maximum input voltage is exceeded, the input D S S DROP OUT current should be limited to ±5mA maximum to prevent where: reducing reliability. A 10kΩ series input resistor, used as a P = total on-chip power D current limiter, will protect the input structure from voltages as P = supply power dissipation S large as 50V above the supply or below ground. See Figure P = output power dissipation 1. O V = V – V S V+ V– I = power supply current S V = V – V (sourcing current) DROP V+ OUT VOUT RIN V = V – V (sinking current) V DROP OUT V– IN 10kΩ The above addresses only steady state (dc) conditions. For Figure 1. Input Current-Limit Protection non-dc conditions the user must estimate power dissipation Output Voltage Swing based on rms value of the signal. Sink and source output resistances of the MIC7300 are The task is one of determining the allowable on-chip power equal. Maximum output voltage swing is determined by the dissipation for operation at a given ambient temperature and load and the approximate output resistance. The output power supply voltage. From this determination, one may resistance is: calculate the maximum allowable power dissipation and, after subtracting P , determine the maximum allowable load V S R = DROP current, which in turn can be used to determine the miniumum OUT ILOAD load impedance that may safely be driven. The calculation is summarized below. V is the voltage dropped within the amplifier output DROP stage. V and I can be determined from the V T − T DROP LOAD O J(max) A (output swing) portion of the appropriate Electrical Character- P = D(max) θ istics table. I is equal to the typical output high voltage JA LOAD minus V+/2 and divided by R . For example, using the θ = 260°C/W LOAD JA(SOT-23-5) Electrical Characteristics DC (5V) table, the typical output θ = 85°C/W JA(MSOP-8) high voltage using a 2kΩ load (connected to V+/2) is 4.985V, which produces an I of: LOAD Driving Capacitive Loads 4.985V − 2.5V 1.243mA Driving a capacitive load introduces phase-lag into the output 2kΩ = . signal, and this in turn reduces op-amp system phase margin. Voltage drop in the amplifier output stage is: The application that is least forgiving of reduced phase margin is a unity gain amplifier. The MIC7300 can typically V = 5.0V – 4.985V DROP drive a 2500pF capacitive load connected directly to the V = 0.015V DROP output when configured as a unity-gain amplifier and pow- Because of output stage symmetry, the corresponding typical ered with a 2.2V supply. At 10V operation the circuit typically output low voltage (0.015V) also equals V . Then: DROP drives 6000pF. Phase margin is typically 40°. 0.015V Using Large-Value Feedback Resistors R = = 12Ω OUT 0.001243A A large-value feedback resistor (> 500kΩ) can reduce the Power Dissipation phase margin of a system. This occurs when the feedback resistor acts in conjunction with input capacitance to create The MIC7300 output drive capability requires considering phase lag in the feedback signal. Input capacitance is usually power dissipation. If the load impedance is low, it is possible a combination of input circuit components and other parasitic to damage the device by exceeding the 125°C junction capacitance, such as amplifier input capacitance and stray temperature rating. printed circuit board capacitance. On-chip power consists of two components: supply power Figure 2 illustrates a method of compensating phase lag and output stage power. Supply power (P ) is the product of S caused by using a large-value feedback resistor. Feedback the supply voltage (V = V – V ) and supply current (I ). S V+ V– S capacitor C introduces sufficient phase lead to overcome FB MIC7300 8 June 2005