Datasheet LT1720, LT1721 (Analog Devices) - 9

LT1720/LT1721
APPLICATIONS INFORMATION High Speed Design Considerations
Although both VCC pins are electrically shorted internal to the LT1721, they must be shorted together externally as Application of high speed comparators is often plagued well in order for both to function as shields. The same is by oscillations. The LT1720/LT1721 have 4mV of internal true for the two GND pins. hysteresis, which will prevent oscillations as long as parasitic output to input feedback is kept below 4mV. The supply bypass should include an adjacent 10nF ce- However, with the 2V/ns slew rate of the LT1720/LT1721 ramic capacitor and a 2.2μF tantalum capacitor no farther outputs, a 4mV step can be created at a 100Ω input source than 5cm away; use more capacitance if driving more with only 0.02pF of output to input coupling. The pinouts than 4mA loads. To prevent oscillations, it is helpful to of the LT1720/LT1721 have been arranged to minimize balance the impedance at the inverting and noninverting problems by placing the most sensitive inputs (invert- inputs; source impedances should be kept low, preferably ing) away from the outputs, shielded by the power rails. 1kΩ or less. The input and output traces of the circuit board should The outputs of the LT1720/LT1721 are capable of very also be separated, and the requisite level of isolation is high slew rates. To prevent overshoot, ringing and other readily achieved if a topside ground plane runs between problems with transmission line effects, keep the output the outputs and the inputs. For multilayer boards where traces shorter than 10cm, or be sure to terminate the lines the ground plane is internal, a topside ground or supply to maintain signal integrity. The LT1720/LT1721 can drive trace should be run between the inputs and outputs, as DC terminations of 250Ω or more, but lower characteristic illustrated in Figure 1. impedance traces can be driven with series termination or AC termination topologies.
Hysteresis
The LT1720/LT1721 include internal hysteresis, which makes them easier to use than many other comparable speed comparators.
(a) (b)
17201 F01 The input-output transfer characteristic is illustrated in
Figure 1. Typical Topside Metal for Multilayer PCB Layouts
Figure 2 showing the defi nitions of VOS and VHYST based Figure 1a shows a typical topside layout of the LT1720 upon the two measurable trip points. The hysteresis band on such a multilayer board. Shown is the topside metal makes the LT1720/LT1721 well behaved, even with slowly etch including traces, pin escape vias, and the land pads moving inputs. for an SO-8 LT1720 and its adjacent X7R 10nF bypass capacitor in a 1206 case. OUTV VOH The ground trace from Pin 5 runs under the device up to the bypass capacitor, shielding the inputs from the out- VHYST (= V + – TRIP – VTRIP ) puts. Note the use of a common via for the LT1720 and the bypass capacitor, which minimizes interference from V high frequency energy running around the ground plane HYST/2 or power distribution traces. VOL + – Figure 1b shows a typical topside layout of the LT1721 $VIN = VIN – VIN on a multilayer board. In this case, the power and ground 0 – + traces have been extended to the bottom of the device VTRIP VTRIP + – solely to act as high frequency shields between input and VTRIP + VTRIP VOS = 2 17201 F02 output traces.
Figure 2. Hysteresis I/O Characteristics
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