Datasheet ATtiny4, ATtiny5, ATtiny9, ATiny10. Summary Datasheet (Microchip) - 9

3. Overview
This device is low-power CMOS 8-bit microcontrollers based on the compact AVR enhanced RISC architecture. By executing powerful instructions in a single clock cycle, the device achieve throughputs approaching 1 MIPS per MHz, allowing the system designer to optimize power consumption versus processing speed.
3.1. Block Diagram Figure 3-1. Block Diagram SRAM CPU FLASH Clock generation Power 8MHz Calib Osc management I/O
PB[3:0]
External clock and clock PORTS control 128 kHz Internal Osc
PCINT[3:0]
D Interrupt
INT0
A T
Vcc
A Watchdog B
ADC[7:0]
Power U Timer ADC
Vcc
S
RESET
Supervision POR & RESET
AIN0 GND
Internal AC
AIN1 ACO
Reference
ADCMUX OC0A/B
TC 0
T0 (16-bit) ICP0
3.1.1. Description
The AVR core combines a rich instruction set with 16 general purpose working registers and system registers. All registers are directly connected to the Arithmetic Logic Unit (ALU), allowing two independent registers to be accessed in one single instruction executed in one clock cycle. The resulting architecture is compact and code efficient while achieving throughputs up to ten times faster than conventional CISC microcontrollers. This device provides the following features: 512/1024 byte of In-System Programmable Flash, 32 bytes of SRAM, four general purpose I/O lines, 16 general purpose working registers, a 16-bit timer/counter with two PWM channels, internal and external interrupts, a programmable watchdog timer with internal oscillator, an internal calibrated oscillator, and four software selectable power saving modes. ATtiny5/10 are also equipped with a four-channel and 8-bit Analog to Digital Converter (ADC). Idle mode stops the CPU while allowing the SRAM, timer/counter, ADC (ATtiny5/10, only), analog comparator, and interrupt system to continue functioning. ADC Noise Reduction mode minimizes switching noise during ADC conversions by stopping the CPU and all I/O modules except the ADC. In Power-down mode registers keep their contents and all chip functions are disabled until the next interrupt Atmel ATtiny4 / ATtiny5 / ATtiny9 / ATiny10 [DATASHEET] 9 Atmel-8127H-ATiny4/ ATiny5 /ATiny9/ ATiny10_Datasheet_Summary-11/2016 Document Outline Introduction Feature Table of Contents 1. Pin Configurations 1.1. Pin Descriptions 1.1.1. VCC 1.1.2. GND 1.1.3. Port B (PB[3:0]) 1.1.4. RESET 2. Ordering Information 2.1. ATtiny4 2.2. ATtiny5 2.3. ATtiny9 2.4. ATtiny10 3. Overview 3.1. Block Diagram 3.1.1. Description 3.2. Comparison of ATtiny4, ATtiny5, ATtiny9 and ATtiny10 4. General Information 4.1. Resources 4.2. Data Retention 4.3. About Code Examples 4.4. Capacitive Touch Sensing 4.4.1. QTouch Library 5. Packaging Information 5.1. 6ST1 5.2. 8MA4 6. Errata 6.1. ATtiny4 6.1.1. Rev. E 6.1.2. Rev. D 6.1.3. Rev. A – C 6.2. ATtiny5 6.2.1. Rev. E 6.2.2. Rev. D 6.2.3. Rev. A – C 6.3. ATtiny9 6.3.1. Rev. E 6.3.2. Rev. D 6.3.3. Rev. A – C 6.4. ATtiny10 6.4.1. Rev. E 6.4.2. Rev. C – D 6.4.3. Rev. A – B