Datasheet ATtiny4, ATtiny5, ATtiny9, ATtiny10. Complete Datasheet (Microchip)

8-bit AVR Microcontroller ATtiny4 / ATtiny5 / ATtiny9 / ATtiny10 DATASHEET COMPLETE Introduction
The Atmel® ATtiny4/5/9/10 is a low-power CMOS 8-bit microcontroller based on the AVR® enhanced RISC architecture. By executing powerful instructions in a single clock cycle, the ATtiny4/5/9/10 achieves throughputs close to 1 MIPS per MHz. This empowers system designer to optimize the device for power consumption versus processing speed.
Feature
• High Performance, Low Power AVR® 8-Bit Microcontroller • Advanced RISC Architecture – 54 Powerful Instructions – Most Single Clock Cycle Execution – 16 x 8 General Purpose Working Registers – Fully Static Operation – Up to 12 MIPS Throughput at 12 MHz • Non-volatile Program and Data Memories – 512/1024 Bytes of In-System Programmable Flash Program Memory – 32 Bytes Internal SRAM – Flash Write/Erase Cycles: 10,000 – Data Retention: 20 Years at 85°C / 100 Years at 25°C • Peripheral Features – QTouch® Library Support for Capacitive Touch Sensing (1 Channel) – One 16-bit Timer/Counter with Prescaler and Two PWM Channels – Programmable Watchdog Timer with Separate On-chip Oscillator – 4-channel, 8-bit Analog to Digital Converter (ATtiny5/10, only) – On-chip Analog Comparator • Special Microcontroller Features – In-System Programmable (at 5V, only) – External and Internal Interrupt Sources Atmel-8127H-ATtiny4 / ATtiny5 / ATtiny9 / ATtiny10_Datasheet_Complete-11/2016 Document Outline Introduction Feature Table of Contents 1. Pin Configurations 1.1. Pin Descriptions 1.1.1. VCC 1.1.2. GND 1.1.3. Port B (PB[3:0]) 1.1.4. RESET 2. Ordering Information 2.1. ATtiny4 2.2. ATtiny5 2.3. ATtiny9 2.4. ATtiny10 3. Overview 3.1. Block Diagram 3.1.1. Description 3.2. Comparison of ATtiny4, ATtiny5, ATtiny9 and ATtiny10 4. General Information 4.1. Resources 4.2. Data Retention 4.3. About Code Examples 4.4. Capacitive Touch Sensing 4.4.1. QTouch Library 5. AVR CPU Core 5.1. Overview 5.2. ALU – Arithmetic Logic Unit 5.3. Status Register 5.4. General Purpose Register File 5.5. The X-register, Y-register, and Z-register 5.6. Stack Pointer 5.7. Instruction Execution Timing 5.8. Reset and Interrupt Handling 5.8.1. Interrupt Response Time 5.9. Register Description 5.9.1. Configuration Change Protection Register 5.9.2. Stack Pointer Register High byte 5.9.3. Stack Pointer Register Low byte 5.9.4. Status Register 6. AVR Memories 6.1. Overview 6.2. In-System Reprogrammable Flash Program Memory 6.3. SRAM Data Memory 6.3.1. Data Memory Access Times 6.4. I/O Memory 7. Clock System 7.1. Clock Distribution 7.2. Clock Subsystems 7.2.1. CPU Clock – clkCPU 7.2.2. I/O Clock – clkI/O 7.2.3. NVM Clock – clkNVM 7.2.4. ADC Clock – clkADC 7.3. Clock Sources 7.3.1. Calibrated Internal 8 MHz Oscillator 7.3.2. External Clock 7.3.3. Internal 128 kHz Oscillator 7.3.4. Switching Clock Source 7.3.5. Default Clock Source 7.4. System Clock Prescaler 7.4.1. Switching Prescaler Setting 7.5. Starting 7.5.1. Starting from Reset 7.5.2. Starting from Power-Down Mode 7.5.3. Starting from Idle / ADC Noise Reduction / Standby Mode 7.6. Register Description 7.6.1. Clock Main Settings Register 7.6.2. Oscillator Calibration Register 7.6.3. Clock Prescaler Register 8. Power Management and Sleep Modes 8.1. Overview 8.2. Sleep Modes 8.2.1. Idle Mode 8.2.2. ADC Noise Reduction Mode 8.2.3. Power-Down Mode 8.2.4. Standby Mode 8.3. Power Reduction Register 8.4. Minimizing Power Consumption 8.4.1. Analog Comparator 8.4.2. Analog to Digital Converter 8.4.3. Watchdog Timer 8.4.4. Port Pins 8.5. Register Description 8.5.1. Sleep Mode Control Register 8.5.2. Power Reduction Register 9. System Control and Reset 9.1. Resetting the AVR 9.2. Reset Sources 9.2.1. Power-on Reset 9.2.2. VCC Level Monitoring 9.2.3. External Reset 9.2.4. Watchdog System Reset 9.3. Watchdog Timer 9.3.1. Overview 9.3.2. Procedure for Changing the Watchdog Timer Configuration 9.3.2.1. Safety Level 1 9.3.2.2. Safety Level 2 9.3.3. Code Examples 9.4. Register Description 9.4.1. Watchdog Timer Control Register 9.4.2. VCC Level Monitoring Control and Status register 9.4.3. Reset Flag Register 10. Interrupts 10.1. Overview 10.2. Interrupt Vectors 10.3. External Interrupts 10.3.1. Low Level Interrupt 10.3.2. Pin Change Interrupt Timing 10.4. Register Description 10.4.1. External Interrupt Control Register A 10.4.2. External Interrupt Mask Register 10.4.3. External Interrupt Flag Register 10.4.4. Pin Change Interrupt Control Register 10.4.5. Pin Change Interrupt Flag Register 10.4.6. Pin Change Mask Register 11. I/O-Ports 11.1. Overview 11.2. Ports as General Digital I/O 11.2.1. Configuring the Pin 11.2.2. Toggling the Pin 11.2.3. Break-Before-Make Switching 11.2.4. Reading the Pin Value 11.2.5. Digital Input Enable and Sleep Modes 11.2.6. Unconnected Pins 11.2.7. Program Example 11.2.8. Alternate Port Functions 11.2.8.1. Alternate Functions of Port B 11.3. Register Description 11.3.1. Port Control Register 11.3.2. Port B Pull-up Enable Control Register 11.3.3. Port B Data Register 11.3.4. Port B Data Direction Register 11.3.5. Port B Input Pins Address 12. 16-bit Timer/Counter0 with PWM 12.1. Features 12.2. Overview 12.2.1. Definitions 12.2.2. Registers 12.3. Accessing 16-bit Registers 12.3.1. Reusing the Temporary High Byte Register 12.4. Timer/Counter Clock Sources 12.4.1. Internal Clock Source - Prescaler 12.4.2. Prescaler Reset 12.4.3. External Clock Source 12.5. Counter Unit 12.6. Input Capture Unit 12.6.1. Input Capture Trigger Source 12.6.2. Noise Canceler 12.6.3. Using the Input Capture Unit 12.7. Output Compare Units 12.7.1. Force Output Compare 12.7.2. Compare Match Blocking by TCNT0 Write 12.7.3. Using the Output Compare Unit 12.8. Compare Match Output Unit 12.8.1. Compare Output Mode and Waveform Generation 12.9. Modes of Operation 12.9.1. Normal Mode 12.9.2. Clear Timer on Compare Match (CTC) Mode 12.9.3. Fast PWM Mode 12.9.4. Phase Correct PWM Mode 12.9.5. Phase and Frequency Correct PWM Mode 12.10. Timer/Counter Timing Diagrams 12.11. Register Description 12.11.1. Timer/Counter0 Control Register A 12.11.2. Timer/Counter0 Control Register B 12.11.3. Timer/Counter0 Control Register C 12.11.4. Timer/Counter0 High byte 12.11.5. Timer/Counter0 Low byte 12.11.6. Output Compare Register 0 A High byte 12.11.7. Output Compare Register 0 A Low byte 12.11.8. Output Compare Register 0 B High byte 12.11.9. Output Compare Register 0 B Low byte 12.11.10. Input Capture Register 0 High byte 12.11.11. Input Capture Register 0 Low byte 12.11.12. Timer/Counter0 Interrupt Mask Register 12.11.13. Timer/Counter0 Interrupt Flag Register 12.11.14. General Timer/Counter Control Register 13. Analog Comparator 13.1. Overview 13.2. Register Description 13.2.1. Analog Comparator Control and Status Register 13.2.2. Digital Input Disable Register 0 14. ADC - Analog to Digital Converter 14.1. Features 14.2. Overview 14.3. Starting a Conversion 14.4. Prescaling and Conversion Timing 14.5. Changing Channel or Reference Selection 14.6. ADC Input Channels 14.7. ADC Voltage Reference 14.8. ADC Noise Canceler 14.9. Analog Input Circuitry 14.10. Analog Noise Canceling Techniques 14.11. ADC Accuracy Definitions 14.12. ADC Conversion Result 14.13. Register Description 14.13.1. ADC Multiplexer Selection Register 14.13.2. ADC Control and Status Register A 14.13.3. ADC Control and Status Register B 14.13.4. ADC Conversion Result Low Byte 14.13.5. Digital Input Disable Register 0 15. Programming interface 15.1. Features 15.2. Overview 15.3. Physical Layer of Tiny Programming Interface 15.3.1. Enabling 15.3.2. Disabling 15.3.3. Frame Format 15.3.4. Parity Bit Calculation 15.3.5. Supported Characters 15.3.6. Operation 15.3.7. Serial Data Reception 15.3.8. Serial Data Transmission 15.3.9. Collision Detection Exception 15.3.10. Direction Change 15.3.11. Access Layer of Tiny Programming Interface 15.3.11.1. Message format 15.3.11.2. Exception Handling and Synchronisation 15.4. Instruction Set 15.4.1. SLD - Serial LoaD from data space using indirect addressing 15.4.2. SST - Serial STore to data space using indirect addressing 15.4.3. SSTPR - Serial STore to Pointer Register 15.4.4. SIN - Serial IN from i/o space using direct addressing 15.4.5. SOUT - Serial OUT to i/o space using direct addressing 15.4.6. SLDCS - Serial LoaD data from Control and Status space using direct addressing 15.4.7. SSTCS - Serial STore data to Control and Status space using direct addressing 15.4.8. SKEY - Serial KEY signaling 15.5. Accessing the Non-Volatile Memory Controller 15.6. Control and Status Space Register Descriptions 15.6.1. Tiny Programming Interface Identification Register 15.6.2. Tiny Programming Interface Physical Layer Control Register 15.6.3. Tiny Programming Interface Status Register 16. MEMPROG- Memory Programming 16.1. Features 16.2. Overview 16.3. Non-Volatile Memories (NVM) 16.3.1. Non-Volatile Memory Lock Bits 16.3.2. Flash Memory 16.3.3. Configuration Section 16.3.3.1. Latching of Configuration Bits 16.3.4. Signature Section 16.3.5. Calibration Section 16.3.5.1. Latching of Calibration Value 16.4. Accessing the NVM 16.4.1. Addressing the Flash 16.4.2. Reading the Flash 16.4.3. Programming the Flash 16.4.3.1. Chip Erase 16.4.3.2. Erasing the Code Section 16.4.3.3. Writing a Code Word 16.4.3.4. Erasing the Configuration Section 16.4.3.5. Writing a Configuration Word 16.4.4. Reading NVM Lock Bits 16.4.5. Writing NVM Lock Bits 16.5. Self programming 16.6. External Programming 16.6.1. Entering External Programming Mode 16.6.2. Exiting External Programming Mode 16.7. Register Description 16.7.1. Non-Volatile Memory Control and Status Register 16.7.2. Non-Volatile Memory Command Register 17. Electrical Characteristics 17.1. Absolute Maximum Ratings* 17.2. DC Characteristics 17.3. Speed 17.4. Clock Characteristics 17.4.1. Accuracy of Calibrated Internal Oscillator 17.4.2. External Clock Drive 17.5. System and Reset Characteristics 17.5.1. Power-On Reset 17.5.2. VCC Level Monitor 17.6. Analog Comparator Characteristics 17.7. ADC Characteristics (ATtiny5/10, only) 17.8. Serial Programming Characteristics 18. Typical Characteristics 18.1. Supply Current of I/O Modules 18.2. Active Supply Current 18.3. Idle Supply Current 18.4. Power-down Supply Current 18.5. Pin Pull-up 18.6. Pin Driver Strength 18.7. Pin Threshold and Hysteresis 18.8. Analog Comparator Offset 18.9. Internal Oscillator Speed 18.10. VLM Thresholds 18.11. Current Consumption of Peripheral Units 18.12. Current Consumption in Reset and Reset Pulsewidth 19. Register Summary 19.1. Note 20. Instruction Set Summary 21. Packaging Information 21.1. 6ST1 21.2. 8MA4 22. Errata 22.1. ATtiny4 22.1.1. Rev. E 22.1.2. Rev. D 22.1.3. Rev. A – C 22.2. ATtiny5 22.2.1. Rev. E 22.2.2. Rev. D 22.2.3. Rev. A – C 22.3. ATtiny9 22.3.1. Rev. E 22.3.2. Rev. D 22.3.3. Rev. A – C 22.4. ATtiny10 22.4.1. Rev. E 22.4.2. Rev. C – D 22.4.3. Rev. A – B 23. Datasheet Revision History 23.1. Rev. 8127H – 11/16 23.2. Rev. 8127G – 09/15 23.3. Rev. 8127F – 02/13 23.4. Rev. 8127E – 11/11 23.5. Rev. 8127D – 02/10 23.6. Rev. 8127C – 10/09 23.7. Rev. 8127B – 08/09 23.8. Rev. 8127A – 04/09