Datasheet ATtiny13A. Summary (Microchip) - 4
| Hersteller | Microchip |
| Beschreibung | 8-bit AVR Microcontroller with 1K Bytes In-System Programmable Flash |
| Seiten / Seite | 20 / 4 — Overview. 2.1. Block Diagram. Figure 2-1. ATtiny13A |
| Dateiformat / Größe | PDF / 591 Kb |
| Dokumentensprache | Englisch |
Overview. 2.1. Block Diagram. Figure 2-1. ATtiny13A
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2. Overview
The ATtiny13A is a low-power CMOS 8-bit microcontroller based on the AVR enhanced RISC architecture. By executing powerful instructions in a single clock cycle, the ATtiny13A achieves throughputs approaching 1 MIPS per MHz allowing the system designer to optimize power con- sumption versus processing speed.
2.1 Block Diagram Figure 2-1.
Block Diagram 8-BIT DATABUS STACK CALIBRATED POINTER INTERNAL WATCHDOG OSCILLATOR OSCILLATOR SRAM WATCHDOG TIMING AND VCC TIMER CONTROL PROGRAM MCU CONTROL REGISTER COUNTER MCU STATUS GND REGISTER PROGRAM FLASH TIMER/ COUNTER0 INSTRUCTION GENERAL REGISTER PURPOSE INTERRUPT REGISTERS UNIT X PROGRAMMING INSTRUCTION Y LOGIC DECODER Z CONTROL DATA LINES ALU EEPROM STATUS REGISTER ADC / DATA REGISTER DATA DIR. ANALOG COMPARATOR PORT B REG.PORT B PORT B DRIVERS RESET CLKI PB[0:5]
4 ATtiny13A
8126FS–AVR–05/12 Document Outline Features 1. Pin Configurations 1.1 Pin Description 1.1.1 VCC 1.1.2 GND 1.1.3 Port B (PB5:PB0) 1.1.4 RESET 2. Overview 2.1 Block Diagram 3. About 3.1 Resources 3.2 Code Examples 3.3 Data Retention 4. Register Summary 5. Instruction Set Summary 6. Ordering Information 7. Packaging Information 7.1 8P3 7.2 8S2 7.3 8S1 7.4 20M1 7.5 10M1 8. Errata 8.1 ATtiny13A Rev. G – H 8.2 ATtiny13A Rev. E – F 8.3 ATtiny13 Rev. A – D 9. Datasheet Revision History 9.1 Rev. 8126F – 05/12 9.2 Rev. 8126E – 07/10 9.3 Rev. 8126D – 11/09 9.4 Rev. 8126C – 09/09 9.5 Rev. 8126B – 11/08 9.6 Rev. 8126A – 05/08
The ATtiny13A is a low-power CMOS 8-bit microcontroller based on the AVR enhanced RISC architecture. By executing powerful instructions in a single clock cycle, the ATtiny13A achieves throughputs approaching 1 MIPS per MHz allowing the system designer to optimize power con- sumption versus processing speed.
2.1 Block Diagram Figure 2-1.
Block Diagram 8-BIT DATABUS STACK CALIBRATED POINTER INTERNAL WATCHDOG OSCILLATOR OSCILLATOR SRAM WATCHDOG TIMING AND VCC TIMER CONTROL PROGRAM MCU CONTROL REGISTER COUNTER MCU STATUS GND REGISTER PROGRAM FLASH TIMER/ COUNTER0 INSTRUCTION GENERAL REGISTER PURPOSE INTERRUPT REGISTERS UNIT X PROGRAMMING INSTRUCTION Y LOGIC DECODER Z CONTROL DATA LINES ALU EEPROM STATUS REGISTER ADC / DATA REGISTER DATA DIR. ANALOG COMPARATOR PORT B REG.PORT B PORT B DRIVERS RESET CLKI PB[0:5]
4 ATtiny13A
8126FS–AVR–05/12 Document Outline Features 1. Pin Configurations 1.1 Pin Description 1.1.1 VCC 1.1.2 GND 1.1.3 Port B (PB5:PB0) 1.1.4 RESET 2. Overview 2.1 Block Diagram 3. About 3.1 Resources 3.2 Code Examples 3.3 Data Retention 4. Register Summary 5. Instruction Set Summary 6. Ordering Information 7. Packaging Information 7.1 8P3 7.2 8S2 7.3 8S1 7.4 20M1 7.5 10M1 8. Errata 8.1 ATtiny13A Rev. G – H 8.2 ATtiny13A Rev. E – F 8.3 ATtiny13 Rev. A – D 9. Datasheet Revision History 9.1 Rev. 8126F – 05/12 9.2 Rev. 8126E – 07/10 9.3 Rev. 8126D – 11/09 9.4 Rev. 8126C – 09/09 9.5 Rev. 8126B – 11/08 9.6 Rev. 8126A – 05/08