Datasheet ATtiny13A. Complete (Microchip) - 8

The fast-access Register File contains 32 x 8-bit general purpose working registers with a single clock cycle access time. This allows single-cycle Arithmetic Logic Unit (ALU) operation. In a typ- ical ALU operation, two operands are output from the Register File, the operation is executed, and the result is stored back in the Register File – in one clock cycle. Six of the 32 registers can be used as three 16-bit indirect address register pointers for Data Space addressing – enabling efficient address calculations. One of the these address pointers can also be used as an address pointer for look up tables in Flash Program memory. These added function registers are the 16-bit X-, Y-, and Z-register, described later in this section. The ALU supports arithmetic and logic operations between registers or between a constant and a register. Single register operations can also be executed in the ALU. After an arithmetic opera- tion, the Status Register is updated to reflect information about the result of the operation. Program flow is provided by conditional and unconditional jump and call instructions, able to directly address the whole address space. Most AVR instructions have a single 16-bit word for- mat. Every Program memory address contains a 16- or 32-bit instruction. During interrupts and subroutine calls, the return address Program Counter (PC) is stored on the Stack. The Stack is effectively allocated in the general data SRAM, and consequently the Stack size is only limited by the total SRAM size and the usage of the SRAM. All user programs must initialize the SP in the Reset routine (before subroutines or interrupts are executed). The Stack Pointer (SP) is read/write accessible in the I/O space. The data SRAM can easily be accessed through the five different addressing modes supported in the AVR architecture. The memory spaces in the AVR architecture are all linear and regular memory maps. A flexible interrupt module has its control registers in the I/O space with an additional Global Interrupt Enable bit in the Status Register. All interrupts have a separate Interrupt Vector in the Interrupt Vector table. The interrupts have priority in accordance with their Interrupt Vector posi- tion. The lower the Interrupt Vector address, the higher the priority. The I/O memory space contains 64 addresses for CPU peripheral functions as Control Regis- ters, SPI, and other I/O functions. The I/O memory can be accessed directly, or as the Data Space locations following those of the Register File, 0x20 - 0x5F.
4.2 ALU – Arithmetic Logic Unit
The high-performance AVR ALU operates in direct connection with all the 32 general purpose working registers. Within a single clock cycle, arithmetic operations between general purpose registers or between a register and an immediate are executed. The ALU operations are divided into three main categories – arithmetic, logical, and bit-functions. Some implementations of the architecture also provide a powerful multiplier supporting both signed/unsigned multiplication and fractional format. See the “Instruction Set” section for a detailed description.
4.3 Status Register
The Status Register contains information about the result of the most recently executed arithme- tic instruction. This information can be used for altering program flow in order to perform conditional operations. Note that the Status Register is updated after all ALU operations, as specified in the Instruction Set Reference. This will in many cases remove the need for using the dedicated compare instructions, resulting in faster and more compact code. The Status Register is not automatically stored when entering an interrupt routine and restored when returning from an interrupt. This must be handled by software.
8 ATtiny13A
8126F–AVR–05/12 Document Outline Features 1. Pin Configurations 1.1 Pin Description 1.1.1 VCC 1.1.2 GND 1.1.3 Port B (PB5:PB0) 1.1.4 RESET 2. Overview 2.1 Block Diagram 3. About 3.1 Resources 3.2 Code Examples 3.3 Data Retention 4. CPU Core 4.1 Architectural Overview 4.2 ALU – Arithmetic Logic Unit 4.3 Status Register 4.3.1 SREG – Status Register 4.4 General Purpose Register File 4.4.1 The X-register, Y-register, and Z-register 4.5 Stack Pointer 4.5.1 SPL – Stack Pointer Low 4.6 Instruction Execution Timing 4.7 Reset and Interrupt Handling 4.7.1 Interrupt Response Time 5. Memories 5.1 In-System Reprogrammable Flash Program Memory 5.2 SRAM Data Memory 5.2.1 Data Memory Access Times 5.3 EEPROM Data Memory 5.3.1 EEPROM Read/Write Access 5.3.2 Atomic Byte Programming 5.3.3 Split Byte Programming 5.3.4 Erase 5.3.5 Write 5.3.6 Preventing EEPROM Corruption 5.4 I/O Memory 5.5 Register Description 5.5.1 EEARL – EEPROM Address Register 5.5.2 EEDR – EEPROM Data Register 5.5.3 EECR – EEPROM Control Register 6. System Clock and Clock Options 6.1 Clock Systems and their Distribution 6.1.1 CPU Clock – clkCPU 6.1.2 I/O Clock – clkI/O 6.1.3 Flash Clock – clkFLASH 6.1.4 ADC Clock – clkADC 6.2 Clock Sources 6.2.1 External Clock 6.2.2 Calibrated Internal 4.8/9.6 MHz Oscillator 6.2.3 Internal 128 kHz Oscillator 6.2.4 Default Clock Source 6.3 System Clock Prescaler 6.3.1 Switching Time 6.4 Register Description 6.4.1 OSCCAL – Oscillator Calibration Register 6.4.2 CLKPR – Clock Prescale Register 7. Power Management and Sleep Modes 7.1 Sleep Modes 7.1.1 Idle Mode 7.1.2 ADC Noise Reduction Mode 7.1.3 Power-down Mode 7.2 Software BOD Disable 7.3 Power Reduction Register 7.4 Minimizing Power Consumption 7.4.1 Analog to Digital Converter 7.4.2 Analog Comparator 7.4.3 Brown-out Detector 7.4.4 Internal Voltage Reference 7.4.5 Watchdog Timer 7.4.6 Port Pins 7.5 Register Description 7.5.1 BODCR – Brown-Out Detector Control Register 7.5.2 MCUCR – MCU Control Register 7.5.3 PRR – Power Reduction Register 8. System Control and Reset 8.1 Resetting the AVR 8.2 Reset Sources 8.2.1 Power-on Reset 8.2.2 External Reset 8.2.3 Brown-out Detection 8.2.4 Watchdog Reset 8.3 Internal Voltage Reference 8.3.1 Voltage Reference Enable Signals and Start-up Time 8.4 Watchdog Timer 8.5 Register Description 8.5.1 MCUSR – MCU Status Register 8.5.2 WDTCR – Watchdog Timer Control Register 9. Interrupts 9.1 Interrupt Vectors 9.2 External Interrupts 9.2.1 Low Level Interrupt 9.2.2 Pin Change Interrupt Timing 9.3 Register Description 9.3.1 MCUCR – MCU Control Register 9.3.2 GIMSK – General Interrupt Mask Register 9.3.3 GIFR – General Interrupt Flag Register 9.3.4 PCMSK – Pin Change Mask Register 10. I/O Ports 10.1 Overview 10.2 Ports as General Digital I/O 10.2.1 Configuring the Pin 10.2.2 Toggling the Pin 10.2.3 Switching Between Input and Output 10.2.4 Reading the Pin Value 10.2.5 Digital Input Enable and Sleep Modes 10.2.6 Unconnected Pins 10.3 Alternate Port Functions 10.3.1 Alternate Functions of Port B 10.4 Register Description 10.4.1 MCUCR – MCU Control Register 10.4.2 PORTB – Port B Data Register 10.4.3 DDRB – Port B Data Direction Register 10.4.4 PINB – Port B Input Pins Address 11. 8-bit Timer/Counter0 with PWM 11.1 Features 11.2 Overview 11.2.1 Registers 11.2.2 Definitions 11.3 Timer/Counter Clock Sources 11.4 Counter Unit 11.5 Output Compare Unit 11.5.1 Force Output Compare 11.5.2 Compare Match Blocking by TCNT0 Write 11.5.3 Using the Output Compare Unit 11.6 Compare Match Output Unit 11.6.1 Compare Output Mode and Waveform Generation 11.7 Modes of Operation 11.7.1 Normal Mode 11.7.2 Clear Timer on Compare Match (CTC) Mode 11.7.3 Fast PWM Mode 11.7.4 Phase Correct PWM Mode 11.8 Timer/Counter Timing Diagrams 11.9 Register Description 11.9.1 TCCR0A – Timer/Counter Control Register A 11.9.2 TCCR0B – Timer/Counter Control Register B 11.9.3 TCNT0 – Timer/Counter Register 11.9.4 OCR0A – Output Compare Register A 11.9.5 OCR0B – Output Compare Register B 11.9.6 TIMSK0 – Timer/Counter Interrupt Mask Register 11.9.7 TIFR0 – Timer/Counter 0 Interrupt Flag Register 12. Timer/Counter Prescaler 12.1 Overview 12.2 Prescaler Reset 12.3 External Clock Source 12.4 Register Description. 12.4.1 GTCCR – General Timer/Counter Control Register 13. Analog Comparator 13.1 Analog Comparator Multiplexed Input 13.2 Register Description 13.2.1 ADCSRB – ADC Control and Status Register 13.2.2 ACSR– Analog Comparator Control and Status Register 13.2.3 DIDR0 – Digital Input Disable Register 0 14. Analog to Digital Converter 14.1 Features 14.2 Overview 14.3 Operation 14.4 Starting a Conversion 14.5 Prescaling and Conversion Timing 14.6 Changing Channel or Reference Selection 14.6.1 ADC Input Channels 14.6.2 ADC Voltage Reference 14.7 ADC Noise Canceler 14.8 Analog Input Circuitry 14.9 Analog Noise Canceling Techniques 14.10 ADC Accuracy Definitions 14.11 ADC Conversion Result 14.12 Register Description 14.12.1 ADMUX – ADC Multiplexer Selection Register 14.12.2 ADCSRA – ADC Control and Status Register A 14.12.3 ADCL and ADCH – The ADC Data Register 14.12.3.1 ADLAR = 0 14.12.3.2 ADLAR = 1 14.12.4 ADCSRB – ADC Control and Status Register B 14.12.5 DIDR0 – Digital Input Disable Register 0 15. debugWIRE On-chip Debug System 15.1 Features 15.2 Overview 15.3 Physical Interface 15.4 Software Break Points 15.5 Limitations of debugWIRE 15.6 Register Description 15.6.1 DWDR –debugWire Data Register 16. Self-Programming the Flash 16.1 Performing Page Erase by SPM 16.2 Filling the Temporary Buffer (Page Loading) 16.3 Performing a Page Write 16.4 Addressing the Flash During Self-Programming 16.5 EEPROM Write Prevents Writing to SPMCSR 16.6 Reading Fuse and Lock Bits from Firmware 16.6.1 Reading Lock Bits from Firmware 16.6.2 Reading Fuse Bits from Firmware 16.7 Preventing Flash Corruption 16.8 Programming Time for Flash when Using SPM 16.9 Register Description 16.9.1 SPMCSR – Store Program Memory Control and Status Register 17. Memory Programming 17.1 Program And Data Memory Lock Bits 17.2 Fuse Bytes 17.2.1 Latching of Fuses 17.3 Calibration Bytes 17.4 Signature Bytes 17.5 Page Size 17.6 Serial Programming 17.6.1 Serial Programming Algorithm 17.6.2 Serial Programming Instruction set 17.7 High-Voltage Serial Programming 17.7.1 High-Voltage Serial Programming Algorithm 17.7.2 High-Voltage Serial Programming Instruction set 17.8 Considerations for Efficient Programming 17.8.1 Chip Erase 17.8.2 Programming the Flash 17.8.3 Programming the EEPROM 17.8.4 Reading the Flash 17.8.5 Reading the EEPROM 17.8.6 Programming and Reading the Fuse and Lock Bits 17.8.7 Reading the Signature Bytes and Calibration Byte 17.8.8 Power-off sequence 18. Electrical Characteristics 18.1 Absolute Maximum Ratings* 18.2 DC Characteristics 18.3 Speed 18.4 Clock Characteristics 18.4.1 Calibrated Internal RC Oscillator Accuracy 18.4.2 External Clock Drive 18.5 System and Reset Characteristics 18.5.1 Enhanced Power-On Reset 18.5.2 Brown-Out Detection 18.6 Analog Comparator Characteristics 18.7 ADC Characteristics 18.8 Serial Programming Characteristics 18.9 High-voltage Serial Programming Characteristics 19. Typical Characteristics 19.1 Supply Current of I/O Modules 19.1.1 Example 19.2 Current Consumption in Active Mode 19.3 Current Consumption in Idle Mode 19.4 Current Consumption in Power-down Mode 19.5 Current Consumption in Reset 19.6 Current Consumption of Peripheral Units 19.7 Pull-up Resistors 19.8 Output Driver Strength (Low Power Pins) 19.9 Output Driver Strength (Regular Pins) 19.10 Input Thresholds and Hysteresis (for I/O Ports) 19.11 BOD, Bandgap and Reset 19.12 Internal Oscillator Speed 20. Register Summary 21. Instruction Set Summary 22. Ordering Information 23. Packaging Information 23.1 8P3 23.2 8S2 23.3 8S1 23.4 20M1 23.5 10M1 24. Errata 24.1 ATtiny13A Rev. G – H 24.2 ATtiny13A Rev. E – F 24.3 ATtiny13 Rev. A – D 25. Datasheet Revision History 25.1 Rev. 8126F – 05/12 25.2 Rev. 8126E – 07/10 25.3 Rev. 8126D – 11/09 25.4 Rev. 8126C – 09/09 25.5 Rev. 8126B – 11/08 25.6 Rev. 8126A – 05/08 Table of Contents