Datasheet LTC2358-18 (Analog Devices)

LTC2358-18 Buffered Octal, 18-Bit, 200ksps/Ch Differential ±10.24V ADC with 30VP-P Common Mode Range
FEATURES DESCRIPTION
n
Simultaneous Sampling of 8 Buffered Channels
The LTC®2358-18 is an 18-bit, low noise 8-channel simul- n
200ksps per Channel Throughput
taneous sampling successive approximation register (SAR) n
500pA/12nA Max Input Leakage at 85°C/125°C
ADC with buffered differential, wide common mode range n
±3.5LSB INL (Maximum, ±10.24V Range)
picoamp inputs. Operating from a 5V low voltage supply, n
Guaranteed 18-Bit, No Missing Codes
flexible high voltage supplies, and using the internal refer- n
Differential, Wide Common Mode Range Inputs
ence and buffer, each channel of this SoftSpanTM ADC can be n
Per-Channel SoftSpan Input Ranges:
independently configured on a conversion-by-conversion n
±10.24V, 0V to 10.24V, ±5.12V, 0V to 5.12V
basis to accept ±10.24V, 0V to 10.24V, ±5.12V, or 0V to n
±12.5V, 0V to 12.5V, ±6.25V, 0V to 6.25V
5.12V signals. Individual channels may also be disabled n
96.4dB Single-Conversion SNR (Typical)
to increase throughput on the remaining channels. n
−111dB THD (Typical) at fIN = 2kHz
The integrated picoamp-input analog buffers, wide input n
128dB CMRR (Typical) at fIN = 200Hz
common mode range and 128dB CMRR of the LTC2358-18 n
Rail-to-Rail Input Overdrive Tolerance
al ow the ADC to directly digitize a variety of signals us- n Integrated Reference and Buffer (4.096V) ing minimal board space and power. This input signal n SPI CMOS (1.8V to 5V) and LVDS Serial I/O flexibility, combined with ±3.5LSB INL, no missing codes n Internal Conversion Clock, No Cycle Latency at 18 bits, and 96.4dB SNR, makes the LTC2358-18 an n 219mW Power Dissipation (27mW/Ch Typical) ideal choice for many high voltage applications requiring n 48-Lead (7mm x 7mm) LQFP Package wide dynamic range. The LTC2358-18 supports pin-selectable SPI CMOS (1.8V
APPLICATIONS
to 5V) and LVDS serial interfaces. Between one and eight lanes of data output may be employed in CMOS mode, n Programmable Logic Controllers allowing the user to optimize bus width and throughput. n Industrial Process Control L, LT, LTC, LTM, Linear Technology and the Linear logo are registered trademarks and n Power Line Monitoring SoftSpan is a trademark of Analog Devices Inc. All other trademarks are the property of their respective owners. Protected by U.S. Patents, including 7705765, 7961132, 8319673, 9197235. n Test and Measurement
TYPICAL APPLICATION
15V 5V 1.8V TO 5V 0.1µF 0.1µF 2.2µF 0.1µF
Integral Nonlinearity vs
CMOS OR LVDS I/O INTERFACE
Output Code and Channel vs Output Code and Channel
FULLY BUFFERS V 2.0 CC VDD VDDLBYP OVDD LVDS/CMOS ±10.24V RANGE ARBITRARY DIFFERENTIAL IN0+ PD TRUE BIPOLAR DRIVE (IN– = 0V) +10V +5V S/H 1.5 IN0– ALL CHANNELS S/H LTC2358-18 0V 0V 1.0 S/H SDO0 • • • –10V –5V 0.5 • • • S/H MUX 18-BIT SDO7 0 TRUE BIPOLAR UNIPOLAR S/H SAR ADC SCKO +10V +10V –0.5 S/H SCKI SDI INL ERROR (LSB) 0V 0V S/H CS –1.0 –10V –10V BUSY SAMPLE IN7+ S/H CNV CLOCK –1.5 IN7– DIFFERENTIAL INPUTS IN+/IN– WITH VEE REFBUF REFIN GND WIDE INPUT COMMON MODE RANGE –2.0 235818 TA01a –131072 –65536 0 65536 131072 EIGHT BUFFERED 47µF 0.1µF 0.1µF OUTPUT CODE SIMULTANEOUS 235818 TA01b SAMPLING CHANNELS –15V 235818f For more information www.linear.com/LTC2358-18 1 Document Outline Features Applications Typical Application Description Absolute Maximum Ratings Order Information Pin Configuration Electrical Characteristics Converter Characteristics Dynamic Accuracy Internal Reference Characteristics Reference Buffer Characteristics Digital Inputs and Digital Outputs Power Requirements ADC Timing Characteristics Typical Performance Characteristics Pin Functions Configuration Tables Functional Block Diagram Timing Diagram Applications Information Board Layout Package Description Typical Application Related Parts