Datasheet NCP1200 (ON Semiconductor) - 10

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NCP1200
VCC Regulation Occurs Here 11.4 V Latchoff 9.8 V Phase 6.3 V Time Drv Driver Driver Pulses Pulses Time Internal Fault Flag Fault is Relaxed Time Startup Phase Fault Occurs Here
Figure 20. If the fault is relaxed during the VCC natural fall down sequence, the IC automatically resumes. If the fault persists when VCC reached UVLOL, then the controller cuts everything off until recovery. Calculating the VCC Capacitor Protecting the Controller Against Negative Spikes
As the above section describes, the fall down sequence As with any controller built upon a CMOS technology, it depends upon the VCC level: how long does it take for the is the designer’s duty to avoid the presence of negative VCC line to go from 11.4 V to 9.8 V? The required time spikes on sensitive pins. Negative signals have the bad habit depends on the startup sequence of your system, i.e. when to forward bias the controller substrate and induce erratic you first apply the power to the IC. The corresponding behaviors. Sometimes, the injection can be so strong that transient fault duration due to the output capacitor charging internal parasitic SCRs are triggered, engendering must be less than the time needed to discharge from 11.4 V irremediable damages to the IC if they are a low impedance to 9.8 V, otherwise the supply will not properly start. The test path is offered between VCC and GND. If the current sense consists in either simulating or measuring in the lab how pin is often the seat of such spurious signals, the much time the system takes to reach the regulation at full high−voltage pin can also be the source of problems in load. Let’s suppose that this time corresponds to 6ms. certain circumstances. During the turn−off sequence, e.g. Therefore a VCC fall time of 10 ms could be well when the user unplugs the power supply, the controller is still appropriated in order to not trigger the overload detection fed by its VCC capacitor and keeps activating the MOSFET circuitry. If the corresponding IC consumption, including ON and OFF with a peak current limited by Rsense. the MOSFET drive, establishes at 1.5 mA, we can calculate Unfortunately, if the quality coefficient Q of the resonating the required capacitor using the following formula: network formed by Lp and Cbulk is low (e.g. the MOSFET Dt + DV @ C, with DV = 2V. Then for a wanted Dt of 10 ms, Rdson + Rsense are small), conditions are met to make the i circuit resonate and thus negatively bias the controller. Since C equals 8 mF or 10 mF for a standard value. When an we are talking about ms pulses, the amount of injected overload condition occurs, the IC blocks its internal charge (Q = I x t) immediately latches the controller which circuitry and its consumption drops to 350 mA typical. This brutally discharges its V appends at V CC capacitor. If this VCC capacitor CC = 9.8 V and it remains stuck until VCC is of sufficient value, its stored energy damages the reaches 6.5 V: we are in latchoff phase. Again, using the controller. Figure 21 depicts a typical negative shot calculated 10 mF and 350 mA current consumption, this occurring on the HV pin where the brutal V latchoff phase lasts: 109 ms. CC discharge testifies for latchup.
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