Datasheet AD7708, AD7718 (Analog Devices)

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8-/10-Channel, Low Voltage, Low Power,
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ADCs AD7708/AD7718 FEATURES GENERAL DESCRIPTION 8-/10-Channel, High Resolution
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ADCs
The AD7708/AD7718 are complete analog front-ends for low
AD7708 Has 16-Bit Resolution
frequency measurement applications. The AD7718 contains a
AD7718 Has 24-Bit Resolution
24-bit Σ-∆ ADC with PGA and can be configured as 4/5 fully-
Factory-Calibrated
differential input channels or 8/10 pseudo-differential input
Single Conversion Cycle Setting
channels. Two pins on the device are configurable as analog
Programmable Gain Front End
inputs or reference inputs. The AD7708 is a 16-bit version of
Simultaneous 50 Hz and 60 Hz Rejection
the AD7718. Input signal ranges from 20 mV to 2.56 V can be
VREF Select™ Allows Absolute and Ratiometric
directly converted using these ADCs. Signals can be converted
Measurement Capability
directly from a transducer without the need for signal conditioning.
Operation Can Be Optimized for
The device operates from a 32 kHz crystal with an on-board PLL
Analog Performance (CHOP = 0) or
generating the required internal operating frequency. The output
Channel Throughput (CHOP = 1)
data rate from the part is software programmable. The peak-to-
INTERFACE
peak resolution from the part varies with the programmed gain
3-Wire Serial
and output data rate.
SPITM, QSPITM, MICROWIRETM, and DSP-Compatible
The part operates from a single 3 V or 5 V supply. When operating
Schmitt Trigger on SCLK
from 3 V supplies, the power dissipation for the part is 3.84 mW typ.
POWER
Both parts are pin-for-pin compatible allowing an upgradable
Specified for Single 3 V and 5 V Operation
path from 16 to 24 bits without the need for hardware modifica-
Normal: 1.28 mA Typ @ 3 V
tions. The AD7708/AD7718 are housed in 28-lead SOIC and
Power-Down: 30
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A (32 kHz Crystal Running)
TSSOP packages.
On-Chip Functions Rail-to-Rail Input Buffer and PGA 2-Bit Digital I/O Port APPLICATIONS Industrial Process Control Instrumentation Pressure Transducers Portable Instrumentation Smart Transmitters FUNCTIONAL BLOCK DIAGRAM DVDD DGND REFIN2(+)/AIN9 REFIN1(+) REFIN2(–)/AIN10 REFIN1(–) XTAL1 XTAL2 OSC AND PLL AIN1 AIN2 POS BUF AIN3 AIN4 REFIN(+) REFIN(–) DOUT AIN5 MUX PGA SERIAL DIN NEG BUF
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ADC* INTERFACE AIN6 SCLK AND AIN7 CS *AD7708 16-BIT ADC CONTROL AIN8 *AD7718 24-BIT ADC LOGIC RDY RESET AVDD AINCOM AD7708/ AD7718 I/O PORT AVDD AGND P2 P1
SPI and QSPI are trademarks of Motorola Inc. MICROWIRE is a trademark of National Semiconductor Corp. VREF Select is a trademark of Analog Devices, Inc. REV. 0 Information furnished by Analog Devices is believed to be accurate and reliable. However, no responsibility is assumed by Analog Devices for its use, nor for any infringements of patents or other rights of third parties that
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