Datasheet STM32F030x4, STM32F030x6, STM32F030x8, STM32F030xC (STMicroelectronics)

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STM32F030x4 STM32F030x6 STM32F030x8 STM32F030xC
Value-line ARM®-based 32-bit MCU with up to 256 KB Flash, timers, ADC, communication interfaces, 2.4-3.6 V operation
Datasheet
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production data Features
• Core: ARM® 32-bit Cortex®-M0 CPU, frequency up to 48 MHz • Memories LQFP64 (10x10 mm) TSSOP20 (6.4x4.4 mm) – 16 to 256 Kbytes of Flash memory LQFP48 (7x7 mm) LQFP32 (7x7 mm) – 4 to 32 Kbytes of SRAM with HW parity • Communication interfaces • CRC calculation unit – Up to two I2C interfaces • Reset and power management – Fast Mode Plus (1 Mbit/s) support on – Digital & I/Os supply: VDD = 2.4 V to 3.6 V one or two I/Fs, with 20 mA current sink – Analog supply: VDDA = VDD to 3.6 V – SMBus/PMBus support (on single I/F) – Power-on/Power down reset (POR/PDR) – Up to six USARTs supporting master – Low power modes: Sleep, Stop, Standby synchronous SPI and modem control; one • Clock management with auto baud rate detection – 4 to 32 MHz crystal oscillator – Up to two SPIs (18 Mbit/s) with 4 to 16 – 32 kHz oscillator for RTC with calibration programmable bit frames – Internal 8 MHz RC with x6 PLL option • Serial wire debug (SWD) – Internal 40 kHz RC oscillator • ® All packages ECOPACK 2 • Up to 55 fast I/Os
Table 1. Device summary
– All mappable on external interrupt vectors – Up to 55 I/Os with 5V tolerant capability
Reference Part number
• 5-channel DMA controller STM32F030x4 STM32F030F4 • One 12-bit, 1.0 µs ADC (up to 16 channels) STM32F030x6 STM32F030C6, STM32F030K6 – Conversion range: 0 to 3.6 V STM32F030x8 STM32F030C8, STM32F030R8 – Separate analog supply: 2.4 V to 3.6 V STM32F030xC STM32F030CC, STM32F030RC • Calendar RTC with alarm and periodic wakeup from Stop/Standby • 11 timers – One 16-bit advanced-control timer for six-channel PWM output – Up to seven 16-bit timers, with up to four IC/OC, OCN, usable for IR control decoding – Independent and system watchdog timers – SysTick timer January 2017 DocID024849 Rev 3 1/91 This is information on a product in full production. www.st.com Document Outline Table 1. Device summary 1 Introduction 2 Description Table 2. STM32F030x4/x6/x8/xC family device features and peripheral counts Figure 1. Block diagram 3 Functional overview 3.1 ARM®-Cortex®-M0 core with embedded Flash and SRAM 3.2 Memories 3.3 Boot modes 3.4 Cyclic redundancy check calculation unit (CRC) 3.5 Power management 3.5.1 Power supply schemes 3.5.2 Power supply supervisors 3.5.3 Voltage regulator 3.5.4 Low-power modes 3.6 Clocks and startup Figure 2. Clock tree 3.7 General-purpose inputs/outputs (GPIOs) 3.8 Direct memory access controller (DMA) 3.9 Interrupts and events 3.9.1 Nested vectored interrupt controller (NVIC) 3.9.2 Extended interrupt/event controller (EXTI) 3.10 Analog to digital converter (ADC) 3.10.1 Temperature sensor Table 3. Temperature sensor calibration values 3.10.2 Internal voltage reference (VREFINT) Table 4. Internal voltage reference calibration values 3.11 Timers and watchdogs Table 5. Timer feature comparison 3.11.1 Advanced-control timer (TIM1) 3.11.2 General-purpose timers (TIM3, TIM14..17) 3.11.3 Basic timers TIM6 and TIM7 3.11.4 Independent watchdog (IWDG) 3.11.5 System window watchdog (WWDG) 3.11.6 SysTick timer 3.12 Real-time clock (RTC) 3.13 Inter-integrated circuit interfaces (I2C) Table 6. Comparison of I2C analog and digital filters Table 7. STM32F030x4/x6/x8/xC I2C implementation 3.14 Universal synchronous/asynchronous receiver/transmitter (USART) Table 8. STM32F0x0 USART implementation 3.15 Serial peripheral interface (SPI) Table 9. STM32F030x4/x6/x8/xC SPI implementation 3.16 Serial wire debug port (SW-DP) 4 Pinouts and pin descriptions Figure 3. LQFP64 64-pin package pinout (top view), for STM32F030x4/6/8 devices Figure 4. LQFP64 64-pin package pinout (top view), for STM32F030RC devices Figure 5. LQFP48 48-pin package pinout (top view), for STM32F030x4/6/8 devices Figure 6. LQFP48 48-pin package pinout (top view), for STM32F030CC devices Figure 7. LQFP32 32-pin package pinout (top view) Figure 8. TSSOP20 20-pin package pinout (top view) Table 10. Legend/abbreviations used in the pinout table Table 11. STM32F030x4/6/8/C pin definitions (continued) Table 12. Alternate functions selected through GPIOA_AFR registers for port A (continued) Table 13. Alternate functions selected through GPIOB_AFR registers for port B Table 14. Alternate functions selected through GPIOC_AFR registers for port C Table 15. Alternate functions selected through GPIOD_AFR registers for port D Table 16. Alternate functions selected through GPIOF_AFR registers for port F 5 Memory mapping Figure 9. STM32F030x4/x6/x8/xC memory map Table 17. STM32F030x4/x6/x8/xC peripheral register boundary addresses (continued) 6 Electrical characteristics 6.1 Parameter conditions 6.1.1 Minimum and maximum values 6.1.2 Typical values 6.1.3 Typical curves 6.1.4 Loading capacitor 6.1.5 Pin input voltage Figure 10. Pin loading conditions Figure 11. Pin input voltage 6.1.6 Power supply scheme Figure 12. Power supply scheme 6.1.7 Current consumption measurement Figure 13. Current consumption measurement scheme 6.2 Absolute maximum ratings Table 18. Voltage characteristics Table 19. Current characteristics Table 20. Thermal characteristics 6.3 Operating conditions 6.3.1 General operating conditions Table 21. General operating conditions (continued) 6.3.2 Operating conditions at power-up / power-down Table 22. Operating conditions at power-up / power-down 6.3.3 Embedded reset and power control block characteristics Table 23. Embedded reset and power control block characteristics (continued) 6.3.4 Embedded reference voltage Table 24. Embedded internal reference voltage 6.3.5 Supply current characteristics Table 25. Typical and maximum current consumption from VDD supply at VDD = 3.6 V Table 26. Typical and maximum current consumption from the VDDA supply Table 27. Typical and maximum consumption in Stop and Standby modes Table 28. Typical current consumption in Run mode, code with data processing running from Flash Table 29. Switching output I/O current consumption 6.3.6 Wakeup time from low-power mode Table 30. Low-power mode wakeup timings 6.3.7 External clock source characteristics Table 31. High-speed external user clock characteristics Figure 14. High-speed external clock source AC timing diagram Table 32. Low-speed external user clock characteristics Figure 15. Low-speed external clock source AC timing diagram Table 33. HSE oscillator characteristics Figure 16. Typical application with an 8 MHz crystal Table 34. LSE oscillator characteristics (fLSE = 32.768 kHz) Figure 17. Typical application with a 32.768 kHz crystal 6.3.8 Internal clock source characteristics Table 35. HSI oscillator characteristics Table 36. HSI14 oscillator characteristics Table 37. LSI oscillator characteristics 6.3.9 PLL characteristics Table 38. PLL characteristics 6.3.10 Memory characteristics Table 39. Flash memory characteristics Table 40. Flash memory endurance and data retention 6.3.11 EMC characteristics Table 41. EMS characteristics Table 42. EMI characteristics 6.3.12 Electrical sensitivity characteristics Table 43. ESD absolute maximum ratings Table 44. Electrical sensitivities 6.3.13 I/O current injection characteristics Table 45. I/O current injection susceptibility 6.3.14 I/O port characteristics Table 46. I/O static characteristics (continued) Figure 18. TC and TTa I/O input characteristics Figure 19. Five volt tolerant (FT and FTf) I/O input characteristics Table 47. Output voltage characteristics Table 48. I/O AC characteristics Figure 20. I/O AC characteristics definition 6.3.15 NRST pin characteristics Table 49. NRST pin characteristics Figure 21. Recommended NRST pin protection 6.3.16 12-bit ADC characteristics Table 50. ADC characteristics (continued) Table 51. RAIN max for fADC = 14 MHz Table 52. ADC accuracy Figure 22. ADC accuracy characteristics Figure 23. Typical connection diagram using the ADC 6.3.17 Temperature sensor characteristics Table 53. TS characteristics 6.3.18 Timer characteristics Table 54. TIMx characteristics Table 55. IWDG min/max timeout period at 40 kHz (LSI) Table 56. WWDG min/max timeout value at 48 MHz (PCLK) 6.3.19 Communication interfaces Table 57. I2C analog filter characteristics Table 58. SPI characteristics Figure 24. SPI timing diagram - slave mode and CPHA = 0 Figure 25. SPI timing diagram - slave mode and CPHA = 1 Figure 26. SPI timing diagram - master mode 7 Package information 7.1 LQFP64 package information Figure 27. LQFP64 outline Table 59. LQFP64 mechanical data (continued) Figure 28. LQFP64 recommended footprint Figure 29. LQFP64 marking example (package top view) 7.2 LQFP48 package information Figure 30. LQFP48 outline Table 60. LQFP48 mechanical data (continued) Figure 31. LQFP48 recommended footprint Figure 32. LQFP48 marking example (package top view) 7.3 LQFP32 package information Figure 33. LQFP32 outline Table 61. LQFP32 mechanical data (continued) Figure 34. LQFP32 recommended footprint Figure 35. LQFP32 marking example (package top view) 7.4 TSSOP20 package information Figure 36. TSSOP20 outline Table 62. TSSOP20 mechanical data (continued) Figure 37. TSSOP20 footprint Figure 38. TSSOP20 marking example (package top view) 7.5 Thermal characteristics Table 63. Package thermal characteristics 7.5.1 Reference document 8 Ordering information Table 64. Ordering information scheme 9 Revision history Table 65. Document revision history (continued)