Datasheet AD711 (Analog Devices) - 8

AD711 OPTIMIZING SETTLING TIME
In addition to a significant improvement in settling time, the Most bipolar high-speed D/A converters have current outputs; low offset voltage, low offset voltage drift, and high open-loop therefore, for most applications, an external op amp is required gain of the AD711 family assures 12-bit accuracy over the full for current-to-voltage conversion. The settling time of the operating temperature range. converter/op amp combination depends on the settling time of The excellent high-speed performance of the AD711 is shown the DAC and output amplifier. A good approximation is: in the oscilloscope photos of Figure 2. Measurements were taken using a low input capacitance amplifier connected directly to the t Total = (t DAC )2 + (t AMP )2 (1) summing junction of the AD711 – both photos show the worst S S S case situation: a full-scale input transition. The DAC’s 4 kW The settling time of an op amp DAC buffer will vary with the [10 kW储8 kW = 4.4 kW] output impedance together with a 10 kW noise gain of the circuit, the DAC output capacitance, and with feedback resistor produce an op amp noise gain of 3.25. The the amount of external compensation capacitance across the current output from the DAC produces a 10 V step at the op DAC output scaling resistor. amp output (0 to –10 V Figure 2a, –10 V to 0 V Figure 2b.) Settling time for a bipolar DAC is typically 100 ns to 500 ns. Therefore, with an ideal op amp, settling to ± 1/2 LSB (± 0.01%) Previously, conventional op amps have required much longer requires that 375 mV or less appears at the summing junction. settling times than have typical state-of-the-art DACs; therefore, This means that the error between the input and output (that the amplifier settling time has been the major limitation to a voltage which appears at the AD711 summing junction) must high-speed voltage-output D-to-A function. The introduction be less than 375 mV. As shown in Figure 2, the total settling time of the AD711/712 family of op amps with their 1 ms (to ± 0.01% for the AD711/AD565 combination is 1.2 microseconds. of final value) settling time now permits the full high-speed capabilities of most modern DACs to be realized.
0.1 F BIPOLAR OFFSET ADJUST R1 REF BIPOLAR 100 OUT VCC OFF 20V R2 SPAN 100 GAIN 10V 10pF ADJUST AD565A 5k 9.95k 10V +15V 19.95k SPAN 0.1 0.5mA F 5k DAC REF IREF IN DAC OUT REF IOUT = 4 AD711K OUTPUT 20k GND I 5k I O REF CODE –10V TO +10V 0.1 F –15V –VEE POWER MSB LSB 0.1 F GND
Figure 1. ±10 V Voltage Output Bipolar DAC a. (Full-Scale Negative Transition) b. (Full-Scale Positive Transition) Figure 2. Settling Characteristics for AD711 with AD565A REV. E –7– Document Outline FEATURES PRODUCT DESCRIPTION CONNECTION DIAGRAMS PRODUCT HIGHLIGHTS SPECIFICATIONS ABSOLUTE MAXIMUM RATINGS ORDERING GUIDE Typical Performance Characteristics OPTIMIZING SETTLING TIME OP AMP SETTLING TIME—A MATHEMATICAL MODEL GUARDING D/A CONVERTER APPLICATIONS NOISE CHARACTERISTICS DRIVING THE ANALOG INPUT OF AN A/D CONVERTER DRIVING A LARGE CAPACITIVE LOAD ACTIVE FILTER APPLICATIONS SECOND ORDER LOW PASS FILTER 9-POLE CHEBYCHEV FILTER OUTLINE DIMENSIONS Revision History