Datasheet Microchip ATSAMA5D27C-CNRVAO — Datenblatt

SAMA5D2 Series
Ultra-Low-Power Arm® Cortex®-A5 Core-Based MPU,
500 MHz, Graphics Interface, Ethernet 10/100, CAN, USB,
PCI 5.0 Pre-Certified
Introduction
The SAMA5D2 series is a high-performance, ultra-low-power Arm Cortex-A5 CPU-based embedded microprocessor
(MPU) running up to 500 MHz, with support for multiple memories such as DDR2, DDR3L, LPDDR2, LPDDR3, and
QSPI and e.MMC Flash. The devices integrate powerful peripherals for connectivity and user interface applications,
®
and offer advanced security functions (Arm TrustZone , tamper detection, secure data storage, etc.), as well as highperformance crypto accelerators AES, SHA and TRNG.
Selected members of the SAMA5D2 series are qualified for extended industrial temperature range operation (-40°C
to 105°C external temperature).
® The SAMA5D2 series is delivered with a free Linux distribution and bare metal C examples. Features
• • • Arm Cortex-A5 Core
– Armv7-A architecture
– Arm TrustZone
™
– NEON Media Processing Engine
– Up to 500 MHz
– ETM/ETB 8 Kbytes
Memory Architecture
– Memory Management Unit (MMU)
– 32-Kbyte L1 data cache, 32-Kbyte L1 instruction cache …

SAMA5D27C AUTO
Ultra-low power ARM Cortex-A5 core-based MPU, 500 MHz,
Graphics Interface, Ethernet 10/100, CAN, USB, Security,
Automotive
Introduction
The SAMA5D27C-CNVAO is a high-performance, ultra-low-power ARM® Cortex®-A5 processor-based MPU running
up to 500 MHz. It offers support for multiple memories such as DDR2, DDR3, DDR3L, LPDDR1, LPDDR2, LPDDR3,
and QSPI Flash and integrates powerful peripherals for connectivity and user interface applications. In addition, it offers
advanced security functions (ARM TrustZone®, tamper detection, secure data storage, etc.), as well as high-performance crypto-processors AES, SHA and TRNG.
Compliant with the international standard ISO-TS-16949, the device is suitable for automotive applications.
The SAMA5D27C-CNVAO is delivered with a free Linux distribution and bare metal C examples. Features
• ARM Cortex-A5 core
-ARMv7-A architecture
-ARM TrustZone
-NEON™ Media Processing Engine
-Up to 500 MHz
-ETM/ETB 8 Kbytes
• Memory Architecture
-Memory Management Unit
-32-Kbyte L1 data cache, 32-Kbyte L1 instruction cache
-128-Kbyte L2 cache configurable to be used as an internal SRAM
-One 128-Kbyte scrambled internal SRAM
-One 160-Kbyte internal ROM 64-Kbyte scrambled and maskable ROM embedding boot loader/ Secure boot loader 96-Kbyte unscrambled, unmaskable ROM for NAND Flash BCH ECC table …