Datasheet Microchip PIC18F57Q84 — Datenblatt

PIC18FXXQ84
PIC18FXXQ84 Family Product Brief
Introduction
The PIC18 Q84 microcontroller family is available in 28/40/44/48-pin devices for many automotive and industrial
applications. The many communication peripherals found on the product family, such as CAN, SPI, I2C, two UARTs,
can handle a wide range of wired and wireless (using external modules) communication protocols for intelligent
applications. This, combined with the Core Independent Peripherals integration capabilities, enable functions for
motor control, power supply, sensor, signal and user interface applications. Additionally, this family includes a 12-bit
ADC with Computation and context saving (ADC3) extensions for automated signal analysis to reduce the complexity
of the application. PIC18 Q84 Family Types Temperature Indicator Peripheral Module Disable Vectored Interrupts 32-Bit CRC with Scanner Windowed Watchdog Timer Direct Memory Access (DMA) UART/
UART with Protocol Support SPI/I2C CAN FD High-Low Voltage Detect Comparator/
Zero-Cross Detect 8-Bit DAC 12-Bit ADC3 (channels) Configurable Logic Cell Numerically Controlled
Oscillator 16-Bit Universal Timer Signal Measurement Timer Complimentary Waveform
Generator 16-Bit Dual PWM/
CCP 8-Bit Timer with HLT/
16-Bit Timers I/O Pins/
Peripheral Pin Select Memory Access Partition/
Device Information Area Data EEPROM
(bytes) Data SRAM
(bytes) Device Program Memory Flash
(bytes) Table 1. Devices Included in This Data Sheet PIC18F26Q84 64k 4096 1024 Y/Y 25/Y 3/3 4/3 3 1 2 3 8 24 1 2/1 1 Y 2/1 3/2 8 Y Y Y Y Y PIC18F27Q84 128k 8192 1024 Y/Y 25/Y 3/3 4/3 3 1 2 3 8 24 1 2/1 1 Y 2/1 3/2 8 Y Y Y Y Y PIC18F46Q84 64k 4096 1024 Y/Y 36/Y 3/3 4/3 3 1 2 3 8 24 1 2/1 1 Y 2/1 3/2 8 Y Y Y Y Y PIC18F47Q84 128k 8192 1024 Y/Y 36/Y 3/3 4/3 3 1 2 3 8 24 1 2/1 1 Y 2/1 3/2 8 Y Y Y Y Y PIC18F56Q84 64k 4096 1024 Y/Y 44/Y 3/3 4/3 3 1 2 3 8 35 1 2/1 1 Y 2/1 3/2 8 Y Y Y Y Y PIC18F57Q84 128k 8192 1024 Y/Y 44/Y 3/3 4/3 3 1 2 3 8 35 1 2/1 1 Y 2/1 3/2 8 Y Y Y Y Y Features
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• • • C Compiler Optimized RISC Architecture …