Datasheet Renesas R5F5651EDDBP#20 — Datenblatt

Features Datasheet RX65N Group, RX651 Group R01DS0276EJ0230
Rev.2.30
Jun 20, 2019 Renesas MCUs 120-MHz 32-bit RX MCU, on-chip FPU, 240 DMIPS, up to 2-MB flash memory
(supportive of the dual bank function), 640-KB SRAM, various communications interfaces including Ethernet MAC,
SD host interface (optional), SD slave interface (optional), quad SPI, and CAN, 12-bit A/D converter, RTC, Encryption
functions (optional), CMOS camera interface, Graphic-LCD controller, 2D drawing engine Features PLQP0176KB-A 24 × 24 mm, 0.5-mm pitch
PLQP0144KA-B 20 × 20 mm, 0.5-mm pitch
PLQP0100KB-B 14 × 14 mm, 0.5-mm pitch
PLQP0064KB-C 10 × 10 mm, 0.5-mm pitch ■ 32-bit RXv2 CPU core  Max. operating frequency: 120 MHz
Capable of 240 DMIPS in operation at 120 MHz
 Single precision 32-bit IEEE-754 floating point
 Two types of multiply-and-accumulation unit (between memories
and between registers)
 32-bit multiplier (fastest instruction execution takes one CPU clock
cycle)
 Divider (fastest instruction execution takes two CPU clock cycles)
 Fast interrupt
 CISC Harvard architecture with 5-stage pipeline
 Variable-length instructions: Ultra-compact code
 Supports the memory protection unit (MPU)
 JTAG and FINE (one-line) debugging interfaces ■ Low-power design and architecture  Operation from a single 2.7-to 3.6-V supply
 Low power consumption: A product that supports all peripheral
functions draws only 0.19 mA/MHz (Typ.). …