Datasheet Microchip PIC16F18425-E/JQ — Datenblatt

PIC16(L)F18425/45
14/20-Pin Full-Featured, Low Pin Count Microcontrollers
with XLP
Description
PIC16(L)F184XX microcontrollers feature Intelligent Analog, Core Independent Peripherals (CIPs) and
communication peripherals combined with eXtreme Low-Power (XLP) for a wide range of general purpose and lowpower applications. Features such as a 12-bit Analog-to-Digital Converter with Computation (ADC2), Memory Access
Partitioning (MAP), the Device Information Area (DIA), Power-Saving operating modes, and Peripheral Pin Select
(PPS), offer flexible solutions for a wide variety of custom applications. Core Features
•
• •
•
•
•
•
•
•
•
• • C Compiler Optimized RISC Architecture
Operating Speed:
– DC – 32 MHz clock input
– 125 ns minimum instruction cycle
Interrupt Capability
16-Level Deep Hardware Stack …

PIC16(L)F184XX
Full-Featured, Low Pin Count Microcontrollers with XLP
Product Brief
Description
PIC16(L)F184XX microcontrollers feature Intelligent Analog, Core Independent Peripherals (CIPs) and
communication peripherals combined with eXtreme Low-Power (XLP) for a wide range of general
purpose and low-power applications. Features such as a 12-bit Analog-to-Digital Converter with
Computation (ADC2), Memory Access Partitioning (MAP), the Device Information Area (DIA), Powersaving operating modes, and Peripheral Pin Select (PPS), offer flexible solutions for a wide variety of
custom applications. Core Features
•
•
• •
•
• •
•
•
•
• • C Compiler Optimized RISC Architecture
Only 48 instructions
Operating Speed:
– DC – 32 MHz clock input
– 125 ns minimum instruction cycle
Interrupt Capability …

PIC16(L)F18425/45
14/20-Pin Full-Featured, Low Pin Count Microcontrollers
with XLP
Description
PIC16(L)F184XX microcontrollers feature Intelligent Analog, Core Independent Peripherals (CIPs) and
communication peripherals combined with eXtreme Low-Power (XLP) for a wide range of general
purpose and low-power applications. Features such as a 12-bit Analog-to-Digital Converter with
Computation (ADC2), Memory Access Partitioning (MAP), the Device Information Area (DIA), Powersaving operating modes, and Peripheral Pin Select (PPS), offer flexible solutions for a wide variety of
custom applications. Core Features
•
•
• •
•
• •
•
•
•
• • C Compiler Optimized RISC Architecture
Only 50 Instructions
Operating Speed:
– DC – 32 MHz clock input
– 125 ns minimum instruction cycle
Interrupt Capability …