Datasheet Texas Instruments TMS320C6201GJC200 — Datenblatt

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Design Kits und Evaluierungsmodule

• JTAG Emulators/ Analyzers: TMDSEMU560V2STM-UE
  XDS560v2 System Trace USB & Ethernet Debug Probe
  Lifecycle Status: Active (Recommended for new designs)
  
• JTAG Emulators/ Analyzers: TMDSEMU560V2STM-U
  XDS560v2 System Trace USB Debug Probe
  Lifecycle Status: Active (Recommended for new designs)
  

Anwendungshinweise

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  TPS5625 Working with TMS320C6201 Applications
  PDF, 65 Kb, Datei veröffentlicht: Oct 28, 1998
  This application report describes a design example that uses fast TPS5625 hysteretic controller and low-cost TL5001A PWM controller installed in SLVP105 and SLVP101 EVMs for a TMS320C6201 DSP application. This design converts 5 V to 2.5 V at 8 A and 3.3 V at 3 A for high-current DSP applications.
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  TMS320C6201 (Revision 2.x) to TMS320C6201B (Revision 3.X) (Rev. A)
  PDF, 39 Kb, Revision: A, Datei veröffentlicht: Sep 2, 1998
  Samples of the Texas Instruments (TIв„ў) TMS320C6201B DSP will be available in the second half of 1998, with volume production starting at the end of the year. The TMS320C6201B revision is manufactured using a 0.18-micron process compared to the currently available revision 2 that uses a 0.25-micron process. The use of a smaller process for the TMS320C6201B DSP will lead to significantly lower
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  Software Development Techniques for the TMS320C6201 DSP
  PDF, 86 Kb, Datei veröffentlicht: Dec 31, 1998
  The advancements in performance and flexibility of modern digital signal processor (DSP) devices is clearly demonstrated in the release of the new TMS320C62xx family of DSPs from Texas Instruments. The TMS320C62xx is a high-performance Very Long Instruction Word (VLIW) DSP based on TIs own Veloci(TI)(tm) architecture. The need to support such an advanced device has fueled a need for DSP develo
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  Setting Up TMS320C6201 Interrupts in C
  PDF, 62 Kb, Datei veröffentlicht: Dec 10, 1998
  How do I set and use interrupts on C for the Texas Instruments (TI)(tm) TMS320C6x DSP?Writing Interrupt Service Routines (ISRs) in C is straightforward as long as you follow the simple rules set out in this document. The problem consists of four parts: - Selecting the interrupt source and writing the ISR- Creating and initializing the interrupt vector table- Setting the proper register
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  TMS320C6201/6701 EVM: TMS320C6000 McBSP to Multimedia Audio Codec (Rev. A)
  PDF, 151 Kb, Revision: A, Datei veröffentlicht: Jul 24, 2001
  This application note describes how a multimedia audio codec can be interfaced to the TMS320C6201/C6701 DSPs. Although this application report uses the CS4231A audio codec as an example, a part that is obsolete, this application note can be used as a reference guide in interfacing similar audio codecs to the TMS320C6000? McBSP. Cirrus Logic offers the CS4235 CrystalClear? ISA audio device that p
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  TMS320C6000 Memory Test (Rev. A)
  PDF, 383 Kb, Revision: A, Datei veröffentlicht: Feb 19, 2002
  This set of programs has been compiled to provide a way to verify the integrity of internal DSP memory and external system memory for all devices currently in the TMS320C6000в„ў (C6000) family. Included with the memory test are all source files, the Code Composer Studio? project file, and the linker command file. The source files contain the necessary parameters to test all devices within the
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  G.729/A Speech Coder: Multichannel TMS320C62x Implementation (Rev. B)
  PDF, 74 Kb, Revision: B, Datei veröffentlicht: Jan 4, 2000
  This document provides a detailed description of the implementation of the G.729 speech encoder and decoder (codec) on the Texas Instruments (TI)(tm) TMS320C6201 digital signal processor (DSP). Topics include program structure, code writing rules, data/program memory requirements, and performance evaluation. Issues regarding multichannel implementation and interrupts are also addressed.Source
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  MPEG-2 Video Decoder: TMS320C62x (TM) DSP Implementation
  PDF, 80 Kb, Datei veröffentlicht: Feb 29, 2000
  This application report describes the implementation of the MPEG-2 video decoder on the TMS320C62x(tm)DSP. The MPEG-2 video standard specifies the decompression and coded representation for entertainment-quality digital video, and is widely used in different digital video systems including DVB, DTV, DVD, DSS, etc. The decoder software implements all the MPEG-2 main-profile-at-main-level functional
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  IS-127 Enhanced Var Rate Speech Coder:Multichannel TMS320C62x Implementation (Rev. B)
  PDF, 92 Kb, Revision: B, Datei veröffentlicht: Jan 4, 2000
  This application report provides a detailed description of the implementation of the IS-12 enhanced variable rate speech codec (EVRC) on the Texas Instrument (TI)(tm) TMS320C62x digital signal processor (DSP). Topics include program structure, code writing rules, data/program memory requirements, and performance evaluation. Issues on multichannel implementation and interrupts are also addressed.
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  On the Implementation of MPEG-4 Motion Compensation Using the TMS320C62x
  PDF, 219 Kb, Datei veröffentlicht: Jul 29, 1999
  This application report describes the implementation of MPEG-4 motion compensation on the Texas Instruments (TI)(tm) TMS320C62x digital signal processor (DSP). MPEG-4 is a standard for coding of audiovisual information being developed by the Motion Picture Experts Group (MPEG). MPEG-4 became an International Standard in December 1998. Motion compensation is a basic component of MPEG-4 and other vi
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  Extended Precision Radix-4 Fast Fourier Transform Implemented on the TMS320C62x
  PDF, 177 Kb, Datei veröffentlicht: Nov 23, 2002
  This paper discusses a method by which the Texas Instruments (TI)(tm) TMS320C62xx or C62xx high performance fixed point DSPs overcome the traditional advantage held by floating point DSPs -- precision and speed.Using the Radix-4 Fast Fourier Transform (FFT), this document illustrates how extended precision arithmetic, multiplication in particular, can be performed on the 'C62xx. Using the te
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  ETSI Math Operations in C for the TMS320C62x (Rev. A)
  PDF, 51 Kb, Revision: A, Datei veröffentlicht: Nov 13, 2000
  Many standard vocoders follow the European Telecommunications Standards Institute (ETSI) for all math operations. One of the purposes of the ETSI math functions is to standardize all math operations into a set of function calls that can be reused by many different vocoders now and in the future.The Global Systems for Mobile Communications (GSM) standard requires vocoders that follow the ETSI s
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  G.723.1 Dual Rate Speech Coder: Multichannel TMS320C62x Implementation (Rev. B)
  PDF, 116 Kb, Revision: B, Datei veröffentlicht: Jan 4, 2000
  This application report describes how the G.723.1 Dual-Rate Speech Coder has been implemented on the TMS320C62x digital signal processor (DSP). Beyond the use of the ?C62x intrinsic functions, the application report includes specific changes required to allow this coder to operate in a real-time system with other speech coders. Also reported is information on several optimization techniques used t
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  TMS320C62x/67x Power Supply Solutions for 1-2 DSPs Using the TL5001A and TPS7133 (Rev. A)
  PDF, 190 Kb, Revision: A, Datei veröffentlicht: Jun 1, 1999
  This application report describes a low-cost power solution for Texas Instruments' TMS320C6000 DSP applications using the TL5001PWM controller and the TPS7133 low drop-out voltage regulator. The reference design included in this report uses the TL5001AEVM-122 (SLVP122) evaluation module (EVM) which is available for customer testing and evaluation.
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  GSM Enhanced Full Rate Speech Coder: Multichannel TMS320C62x Implementation (Rev. B)
  PDF, 83 Kb, Revision: B, Datei veröffentlicht: Jan 4, 2000
  This document provides a detailed description of the implementation of the GSM enhanced full rate (EFR) speech encoder and decoder (codec) on the Texas Instruments (TI)(tm)TMS320C62x digital signal processor (DSP). Topics include program structure, code writing rules, data/program memory requirement, and performance evaluation. Issues on multichannel implementation and interrupts are also addresse
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  TMS320C6000 DMA Example Applications (Rev. A)
  PDF, 864 Kb, Revision: A, Datei veröffentlicht: Apr 10, 2002
  The TMS320C6000? on-chip direct memory access (DMA) controller from Texas Instruments is used to transfer data between two locations in the memory map in the background of CPU operation. Typically, the DMA is used to:Transfer blocks of data between external and internal data memoriesRestructure portions of internal data memoryContinually service a peripheralPage program s
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  Using TI FIFOs to Interface High-Speed Data Converters With TI TMS320 DSPs
  PDF, 249 Kb, Datei veröffentlicht: Jun 8, 2001
  Most high-speed data converters cannot be connected directly to a digital signal processor (DSP). The required transfer rates would tie up most of the DSP's I/O bandwidth. A FIFO is an appropriate solution for this problem because it can buffer a large block of data, and the DSP can read data from the FIFO in a burst mode. This is much more efficient compared to single reads for every sampled valu
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  TMS320C620x/C642x McBSP: UART (Rev. C)
  PDF, 293 Kb, Revision: C, Datei veröffentlicht: Sep 9, 2008
  This document describes how to use the multichannel buffered serial port (McBSP) in the Texas Instruments (TI) TMS320C6000в„ў (C6000в„ў) digital signal processors (DSP) to interface to a universal asynchronous receiver/transmitter (UART). Descriptions of the hardware configuration and software routines necessary for proper functionality are included.The McBSP is not capable of support
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  TMS320C6000 HPI to PCI Interfacing Using the PLX PCI9050 (Rev. C)
  PDF, 248 Kb, Revision: C, Datei veröffentlicht: Apr 17, 2002
  This application report describes an interface between the Texas Instruments TMS320C6000в„ў DSP host port and the PLX Technology PCI9050 (PCI9052), the PCI interface chip. The PCI9052 is functionally the same as the PCI9050. The only difference between these two devices is that the PCI9052 is somewhat faster than the PCI9050.This application report includes a diagram showing connections be
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  TMS320C6000 Host Port to the i80960 Microprocessors Interface (Rev. A)
  PDF, 272 Kb, Revision: A, Datei veröffentlicht: Aug 31, 2001
  This application report describes the interface between the Texas Instruments (TI) TMS320C6000в„ў digital signal processor (DSP) host port and the Intel 80960 microprocessor. The document includes schematics showing connections between the two devices, PAL equations, and verification that timing requirements are met for each device (tables and timing diagrams).
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  TMS320C6000 Host Port to MC68360 Interface (Rev. A)
  PDF, 261 Kb, Revision: A, Datei veröffentlicht: Sep 30, 2001
  This application report describes an interface between the Motorola MC68360 quad integrated communication controller (QUICC) and the host port interface (HPI) of a TMS320C6000в„ў (C6000в„ў) digital signal processor (DSP) device. This includes a schematic showing connections between the two devices and verification that timing requirements are met for each device (tables and timing diagrams
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  TMS320C6000 Host Port to MPC860 Interface (Rev. A)
  PDF, 311 Kb, Revision: A, Datei veröffentlicht: Jun 21, 2001
  This application report describes an interface between the Motorola MPC860 microprocessor and the host port interface (HPI) of a Texas Instruments TMS320C6000в„ў (C6000в„ў) digital signal processor (DSP) device. This document includes a schematic showing connections between the two devices, PAL equations, and verification that timing requirements are met for each device (tables and timing
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  Interfacing theTMS320C6000 EMIFto a PCI Bus Using the AMCC S5933 PCI Controller (Rev. A)
  PDF, 309 Kb, Revision: A, Datei veröffentlicht: Sep 30, 2001
  This application report describes the architecture and capabilities of the AMCC S5933 PCI controller and how it can be interfaced to the TMS320C6201 digital signal processor (DSP). The DSP's host port interface (HPI) can be a PCI target, and its external memory interface (EMIF) can be used to support PCI bus mastering. Details on the signals and logic required to implement both PCI slave and maste
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  TMS320C6000 System Clock Circuit Example (Rev. A)
  PDF, 129 Kb, Revision: A, Datei veröffentlicht: Aug 15, 2001
  This document describes how to provide the Texas Instruments TMS320C6000в„ў DSP with a system clock. All of the clocks internal to the C6000в„ў are generated from a single source through the CLKIN pin. This source clock for the device is an external signal that, depending on the clock mode, either drives the on-chip Phase-Locked Loop (PLL) circuit, which multiplies the source clock in freq
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  TMS320C6000 McBSP: I2S Interface
  PDF, 93 Kb, Datei veröffentlicht: Sep 8, 1999
  This document describes how to use the multichannel buffered serial port (McBSP) in the Texas Instruments (TI)(TM) TMS320C6000 digital signal processors (DSP) to interface with devices that conform to the Inter-IC Sound (I2S) specification. I2S is a protocol for transmitting two channels of digital audio data over a single serial connection.The flexible McBSP in the TMS320C6000 supports the I
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  General Guide to Implement Logarithmic and Exponential Operations on Fixed-Point
  PDF, 50 Kb, Datei veröffentlicht: Jan 31, 2000
  Modern audio and video compression algorithms usually take the advantage of logarithmic characteristics of human ears and eyes. This approach greatly reduces the redundancy in signals being processed. However, it poses a requirement on fixed-point DSPs to handle these logarithmic and exponential operations.This application report provides a general guide to implement these operations on fixed-
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  TMS320C6000 McBSP: AC'97 Codec Interface (TLV320AIC27) (Rev. A)
  PDF, 289 Kb, Revision: A, Datei veröffentlicht: Jul 10, 2001
  This document describes how to use the multichannel buffered serial ports (McBSPs) in the Texas Instruments TMS320C6000в„ў digital signal processor (DSP) as a digital controller for an audio codec 1997 device.The McBSP is connected to a stereo audio codec 1997 device. This application report uses the TLV320AIC27 audio codec (AIC27) as an example. The audio codec 1997 (AC'97) standard spec
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  TMS320C6000 Board Design for JTAG (Rev. C)
  PDF, 89 Kb, Revision: C, Datei veröffentlicht: Apr 2, 2002
  Designing a TMS320C6000в„ў DSP board to utilize all of the functionality of the JTAG scan path is a simple process, but a few considerations must be taken into account. The default state of the emulation signals determines whether the JTAG port is used for emulation or for boundary scan. It is therefore necessary to provide flexibility in the design to accommodate those modes that are desired.
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  Circular Buffering on TMS320C6000 (Rev. A)
  PDF, 172 Kb, Revision: A, Datei veröffentlicht: Sep 12, 2000
  This application report explains how circular buffering is implemented on the TMS320C6000? devices. Circular buffering helps to implement finite impulse response (FIR) filters efficiently. Filters require delay lines or buffers of past (and current) samples. Circular addressing simplifies the manipulation of pointers in accessing the data samples.This application report addresses the following
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  TMS320C6000 Board Design: Considerations for Debug (Rev. C)
  PDF, 96 Kb, Revision: C, Datei veröffentlicht: Apr 21, 2004
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  Using a TMS320C6000 McBSP for Data Packing (Rev. A)
  PDF, 257 Kb, Revision: A, Datei veröffentlicht: Oct 31, 2001
  This application report describes how to use the multichannel buffered serial port (McBSP) in the Texas Instruments TMS320C6000в„ў digital signal processor (DSP) for data packing. Data packing involves moving either multiple successive 8-bit elements to/from the McBSP as a single 16/24/32-bit element or multiple successive 16-bit words to/from the McBSP as a single 32-bit word.The McBSP
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  TMS320C6000 McBSP Initialization (Rev. C)
  PDF, 232 Kb, Revision: C, Datei veröffentlicht: Mar 8, 2004
  The TMS320C6000? multichannel buffered serial port (McBSP) can operate in a variety of modes, as per application requirements. For proper operation, the serial port must be initialized in a specific order. This document describes the initialization steps necessary when either the (E)DMA or the CPU is used to service the McBSP data. Typically, the (E)DMA is used to perform read/write transfers from
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  TMS320C6000 EMIF to External Asynchronous SRAM Interface (Rev. A)
  PDF, 118 Kb, Revision: A, Datei veröffentlicht: Aug 31, 2001
  Interfacing external asynchronous static RAM (ASRAM) to the Texas Instruments (TIв„ў) TMS320C6000 series of digital signal processors (DSPs) is simple compared to previous generations of TI DSPs, thanks to the advanced external memory interface (EMIF). The EMIF provides a glueless interface to a variety of external memory devices.This document describes:EMIF control registers and ASR
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  TMS320C6000 EMIF to External Flash Memory (Rev. A)
  PDF, 471 Kb, Revision: A, Datei veröffentlicht: Feb 13, 2002
  Interfacing external flash memory to the Texas Instruments TMS320C6000в„ў digital signal processor (DSP) is simple compared to previous generations of TI DSPs. The TMS320C6000 advanced external memory interface (EMIF) provides a glueless interface to a variety of external memory devices.This document describes the following:EMIF control registers and asynchronous interface signals<
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  TMS320C6000 C Compiler: C Implementation of Intrinsics
  PDF, 154 Kb, Datei veröffentlicht: Dec 7, 1999
  The first optimization step that you can perform on C source code for the TMS320C62xx is to use intrinsic operators. Intrinsics are used like functions and produce assembly language statements that would otherwise be inexpressible in C. The problem is that once you have performed the first optimization step, your C source code is no longer ANSI C compatible. The code proposed within this appli
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  TMS320C6000 McBSP: IOM-2 Interface (Rev. A)
  PDF, 284 Kb, Revision: A, Datei veröffentlicht: May 21, 2001
  This document describes how the multi-channel buffered serial port (McBSP) in the Texas Instruments (TI) TMS320C6000? (C6000?) digital signal processor (DSP) family is used to communicate to an ISDN Oriented Modular Interface Revision 2 (IOM-2) bus-compliant device. This document also describes the usage of McBSP registers and sample code to perform the above function.
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  TMS320C6000 McBSP: Interface to SPI ROM (Rev. C)
  PDF, 99 Kb, Revision: C, Datei veröffentlicht: Jun 30, 2001
  The TMS320C6000? (C6000?) Multichannel Buffered Serial Port (McBSP) is designed to interface to a device that supports synchronous Serial Peripheral Interface (SPI). This document describes the hardware interface between the McBSP and a SPI ROM. The McBSP operates as the master in a user-specified clock stop (CLKSTP) mode in order to communicate with the SPI ROM. The McBSP initialization and contr
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  TMS320C6000 EMIF-to-External SDRAM Interface (Rev. E)
  PDF, 833 Kb, Revision: E, Datei veröffentlicht: Sep 4, 2007
  Interfacing external SDRAM to the Texas Instruments TMS320C6000™ digital signal processor (DSP) is simple, compared to previous generations of TI DSPs, because of the advanced external memory interface (EMIF). The EMIF is a glueless interface to a variety of external memory devices.This application report describes the EMIF’s control registers and SDRAM signals along with SDRAM function
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  TMS320C6000 Tools: Vector Table and Boot ROM Creation (Rev. D)
  PDF, 185 Kb, Revision: D, Datei veröffentlicht: Apr 26, 2004
  Texas Instruments TMS320C6000в„ў digital signal processors (DSPs) provide a variety of boot configurations that determine which actions are performed after device reset, to prepare for initialization. The boot process is determined by latching the boot configuration settings at reset.The boot process performed by the DSP is to either load code from an external read-only memory (ROM) space
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  Using the TMS320C6000 McBSP as a High Speed Communication Port (Rev. A)
  PDF, 296 Kb, Revision: A, Datei veröffentlicht: Aug 31, 2001
  This document describes how to use the mulit-channel buffered serial ports (McBSP) in the Texas Instruments (TI) TMS320C6000в„ў digital signal processor (DSP) as a high-speed data communication port.One McBSP of one C6000в„ў DSP device can be connected to a McBSP on another C6000 DSP device to serve as a high-speed data communication port. Typically, McBSPs of similar device numbers a
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  TMS320C6000 McBSP to Voice Band Audio Processor (VBAP) Interface (Rev. A)
  PDF, 240 Kb, Revision: A, Datei veröffentlicht: Jul 23, 2001
  This document describes how to interface the multichannel buffered serial port (McBSP) in the TMS320C6000? digital signal processor (DSP) to a voice band audio processor (VBAP). The VBAP under discussion is the TI TLV320AC56, 3V, 2.048 MHz audio processor which is a m-law companding device. The interface is also applicable to TI?s TLV320AC57, an A-law companding audio processor.The highly
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  TMS320C6000 u-Law and a-Law Companding with Software or the McBSP
  PDF, 150 Kb, Datei veröffentlicht: Feb 2, 2000
  This document describes how to perform data companding with the TMS320C6000(tm)digital signal processors(DSP). Companding refers to the compression and expansion of transfer data before and after transmission, respectively.The multichannel buffered serial port (McBSP) in the TMS320C6000 supports two companding formats: mu-Law and A-Law. Both companding formats are specified in the CCITT G.711
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  TMS320C6000 McBSP as a TDM Highway (Rev. A)
  PDF, 313 Kb, Revision: A, Datei veröffentlicht: Sep 11, 2000
  This document describes how the multichannel buffered serial ports (McBSP) in the TMS320C6000в„ў digital signal processors (DSP) are used to communicate on a time-division multiplexed (TDM) data highway.TDM provides multiple devices a time slot to perform data transfer. Thus, multiple users operate various channels; however, each user has a set of channel(s) assigned for transmission and re
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  TMS320C6000 McBSP Interface to an ST-BUS Device (Rev. B)
  PDF, 87 Kb, Revision: B, Datei veröffentlicht: Jun 4, 2002
  This document describes how the multichannel buffered serial ports (McBSPs) in the Texas Instruments TMS320C6000в„ў digital signal processor (DSP) are used to communicate to a single-rate Serial Telecom (ST)-BUS-compliant device.The McBSP receives the framing signal, clock, and data from the ST-BUSв„ў device and processes them to generate internal frame syncs and clocks for correct data
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  Using IBIS Models for Timing Analysis (Rev. A)
  PDF, 301 Kb, Revision: A, Datei veröffentlicht: Apr 15, 2003
  Today?s high-speed interfaces require strict timings and accurate system design. To achieve the necessary timings for a given system, input/output buffer information specification (IBIS) models must be used. These models accurately represent the device drivers under various process conditions. Board characteristics, such as impedance, loading, length, number of nodes, etc., affect how the device d
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  Thermal Considerations for the DM64xx, DM64x, and C6000 Devices
  PDF, 127 Kb, Datei veröffentlicht: May 20, 2007
  As integrated circuit (IC) components become more complex, the challenge of producing an end product with superior thermal performance increases. Thermal performance is a system level concern, impacted by IC packaging as well as by printed circuit board (PCB) design. This application report addresses the thermal considerations for the TMS320DM64xx, TMS320DM64x, and TMS320C6000в„ў DSP devices.

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