Datasheet Texas Instruments CD74AC573E — Datenblatt

HerstellerTexas Instruments
SerieCD74AC573
ArtikelnummerCD74AC573E
Datasheet Texas Instruments CD74AC573E

Oktale transparente nicht invertierende Latches mit 3-Zustands-Ausgängen 20-PDIP -55 bis 125

Datenblätter

Octal Transparent Latch, 3-State datasheet
PDF, 1.3 Mb, Datei veröffentlicht: Dec 3, 1998
Auszug aus dem Dokument

Preise

Status

Lifecycle StatusActive (Recommended for new designs)
Manufacture's Sample AvailabilityNo

Verpackung

Pin20
Package TypeN
Industry STD TermPDIP
JEDEC CodeR-PDIP-T
Package QTY20
CarrierTUBE
Device MarkingCD74AC573E
Width (mm)6.35
Length (mm)24.33
Thickness (mm)4.57
Pitch (mm)2.54
Max Height (mm)5.08
Mechanical DataHerunterladen

Parameter

3-State OutputYes
Bits8
F @ Nom Voltage(Max)100 Mhz
ICC @ Nom Voltage(Max)0.08 mA
Operating Temperature Range-55 to 125 C
Output Drive (IOL/IOH)(Max)24/-24 mA
Package GroupPDIP
Package Size: mm2:W x LSee datasheet (PDIP) PKG
RatingCatalog
Schmitt TriggerNo
Technology FamilyAC
VCC(Max)5.5 V
VCC(Min)1.5 V
Voltage(Nom)1.5,3.3,5 V
tpd @ Nom Voltage(Max)119,13.4,9.5 ns

Öko-Plan

RoHSCompliant
Pb FreeYes

Anwendungshinweise

  • Power-Up Behavior of Clocked Devices (Rev. A)
    PDF, 34 Kb, Revision: A, Datei veröffentlicht: Feb 6, 2015
  • Using High Speed CMOS and Advanced CMOS in Systems With Multiple Vcc
    PDF, 43 Kb, Datei veröffentlicht: Apr 1, 1996
    Though low power consumption is a feature of CMOS devices sometimes this feature does not meet a designer?s system power supply constraints. Therefore a partial system power down or multiple Vcc supplies are used to meet the needs of the system. This document shows electrostatic discharge protection circuits. It also provides circuit and bus driver examples of partial system power down and curren

Modellreihe

Herstellerklassifikation

  • Semiconductors > Logic > Flip-Flop/Latch/Register > D-Type Latch