Datasheet Microchip KSZ9031RNXIA — Datenblatt

KSZ9031MNX
Gigabit Ethernet Transceiver with GMII/MII
Support
Features Target Applications Single-Chip 10/100/1000 Mbps Ethernet Transceiver Suitable for IEEE 802.3 Applications GMII/MII Standard Interface with 3.3V/2.5V/1.8V
Tolerant I/Os Auto-Negotiation to Automatically Select the
Highest Link-Up Speed (10/100/1000 Mbps) and
Duplex (Half/Full) On-Chip Termination Resistors for the Differential
Pairs On-Chip LDO Controller to Support Single 3.3V
Supply Operation Jumbo Frame Support Up to 16 KB 125 MHz Reference Clock Output Energy-Detect Power-Down Mode for Reduced
Power Consumption When the Cable is Not
Attached Wake-On-LAN (WOL) Support with Robust Custom-Packet Detection Programmable LED Outputs for Link, Activity, and
Speed Baseline Wander Correction LinkMD TDR-based Cable Diagnostic to Identify
Faulty Copper Cabling Parametric NAND Tree Support to Detect Faults
Between Chip I/Os and Board Loopback Modes for Diagnostics Automatic MDI/MDI-X Crossover to Detect and
Correct Pair Swap at All Speeds of Operation Automatic Detection and Correction of Pair
Swaps, Pair Skew, and Pair Polarity MDC/MDIO Management Interface for PHY Register Configuration Interrupt Pin Option Power-Down and Power-Saving Modes Operating Voltages
-Core (DVDDL, AVDDL, AVDDL_PLL): 1.2V
(External FET or Regulator)
-VDD I/O (DVDDH): 3.3V, 2.5V, or 1.8V
-Transceiver (AVDDH): 3.3V or 2.5V
(Commercial Temp.) 64-pin QFN (8 mm Г— 8 mm) Package пѓЈ 2016-2017 Microchip Technology Inc. Laser/Network Printer
Network Attached Storage (NAS)
Network Server …

KSZ9031RNX
Gigabit Ethernet Transceiver with RGMII
Support
Features Single-Chip 10/100/1000 Mbps Ethernet Transceiver Suitable for IEEE 802.3 Applications RGMII Timing Supports On-Chip Delay According
to RGMII Version 2.0, with Programming Options
for External Delay and Making Adjustments and
Corrections to TX and RX Timing Paths RGMII with 3.3V/2.5V/1.8V Tolerant I/Os Auto-Negotiation to Automatically Select the
Highest Link-Up Speed (10/100/1000 Mbps) and
Duplex (Half/Full) On-Chip Termination Resistors for the Differential
Pairs On-Chip LDO Controller to Support Single 3.3V
Supply Operation – Requires Only One External
FET to Generate 1.2V for the Core Jumbo Frame Support up to 16 KB 125 MHz Reference Clock Output Energy Detect Power-Down Mode for Reduced
Power Consumption When the Cable is Not
Attached Wake-On-LAN (WOL) Support with Robust Custom-Packet Detection Programmable LED Outputs for Link, Activity, and
Speed Baseline Wander Correction LinkMD TDR-Based Cable Diagnostic to Identify
Faulty Copper Cabling Parametric NAND Tree Support to Detect Faults
Between Chip I/Os and Board Loopback Modes for Diagnostics Automatic MDI/MDI-X Crossover to Detect and
Correct Pair Swap at all Speeds of Operation Automatic Detection and Correction of Pair
Swaps, Pair Skew, and Pair Polarity MDC/MDIO Management Interface for PHY Register Configuration Interrupt Pin Option Power-Down and Power-Saving Modes пѓЈ 2016-2017 Microchip Technology Inc. Operating Voltages
-Core (DVDDL, AVDDL, AVDDL_PLL): 1.2V
(External FET or Regulator)
-VDD I/O (DVDDH): 3.3V, 2.5V, or 1.8V
-Transceiver (AVDDH): 3.3V or 2.5V (Commercial Temp.) AEC-Q100 Grade 3 (KSZ9031RNXUA/UB) and …