Datasheet Microchip PL500-37 — Datenblatt

(Preliminary) PL500-37 Low Phase Noise VCXO (36MHz to 130MHz)
FEATURES
п‚ п‚ VCXO output for the 36MHz to 130MHz range
Low phase noise (-148 dBc @ 10kHz offset at
77.76MHz).
CMOS output with OE tri -state control.
36 to 130MHz fundamental crystal input.
Integrated high linearity variable capacitors.
8mA drive capability at TTL output.
+/-150 ppm pull range, max 5% linearity.
Low jitter (RMS): 2.5ps period jitter.
Single 2.5V В±10% or 3.3V В±10 power supply.
Operating temperature range from -40п‚°C to +85п‚°C
Available in Die or Wafer form or SOP-8L or
SOT23-6L packaging. XIN 1 OE^ 2 VCON 3 GND 4 PL500-37 8 XOUT 7 DNC 6 VDD 5 CLK SOP-8L VCON 1 GND 2 XIN 3 P500-37 п‚ п‚ п‚ п‚ п‚ п‚ п‚ п‚ п‚ PIN AND PAD CONFIGURATION 6 CLK 5 VDD 4 XOUT SOT23-6L DESCRIPTION
The PL500-37 is a low cost, high performance and
low phase noise VCXO for the 36 to 130MHz range,
providing less than -148dBc at 10kHz offset at
77.76MHz. The very low jitter (2.5 ps RMS period
jitter) makes this chip ideal for applications requiring
voltage controlled frequency sources. The input
crystal frequency can range from 36 to 130MHz
(fundamental resonant mode). ^: Denotes internal Pull-up 32 mil 8 …